From b9507768128077d0a99f45bd3dbf5e934e32c492 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 21 Mar 2025 19:24:08 -0700 Subject: [PATCH 1/5] standalone fix to generate sve mov instead of NEON mov --- src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 2751839a89b546..3a52e6371e3fe4 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -1857,6 +1857,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) break; } + case NI_Vector_ToScalar: case NI_Vector64_ToScalar: case NI_Vector128_ToScalar: { @@ -2544,8 +2545,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) assert((targetReg == op2Reg) || (targetReg != op1Reg)); assert((targetReg == op2Reg) || (targetReg != op3Reg)); - GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op2Reg, - /* canSkip */ true); + GetEmitter()->emitIns_Mov(INS_sve_mov, EA_SCALABLE, targetReg, op2Reg, /* canSkip */ true, opt); GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op3Reg, opt, INS_SCALABLE_OPTS_NONE); break; @@ -2561,8 +2561,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) assert(varTypeIsFloating(node->gtType) || varTypeIsSIMD(node->gtType)); assert((targetReg == op2Reg) || (targetReg != op1Reg)); assert((targetReg == op2Reg) || (targetReg != op3Reg)); - GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg, - /* canSkip */ true); + + GetEmitter()->emitIns_Mov(INS_sve_mov, EA_SCALABLE, targetReg, op2Reg, /* canSkip */ true, opt); GetEmitter()->emitInsSve_R_R_R(ins, EA_SCALABLE, targetReg, op1Reg, op3Reg, opt, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); break; From a9e9a9cfd40fc80581bc992faa21292f3d583bd8 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 24 Mar 2025 14:54:43 -0700 Subject: [PATCH 2/5] standalone fix to generate ldr/str when emit_RR is called --- src/coreclr/jit/emitarm64sve.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/emitarm64sve.cpp b/src/coreclr/jit/emitarm64sve.cpp index 62e767d6320525..e04fd2d42ab151 100644 --- a/src/coreclr/jit/emitarm64sve.cpp +++ b/src/coreclr/jit/emitarm64sve.cpp @@ -2256,7 +2256,14 @@ void emitter::emitInsSve_R_R(instruction ins, // Thus, MOV is the preferred disassembly. ins = INS_sve_mov; break; - + case INS_sve_ldr: + case INS_sve_str: + { + // We might come here through emitIns_R_R() to emit "ldr Zx, [Xn]" and + // in the case, just generate the ldr variant, where offset is zero. + emitInsSve_R_R_I(ins, attr, reg1, reg2, 0, opt, sopt); + return; + } default: unreached(); break; From 45356948824427a5b4752a663e871e6b3a5e3417 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 24 Mar 2025 15:34:31 -0700 Subject: [PATCH 3/5] Remove unwanted change --- src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 3a52e6371e3fe4..d97b16bcf0cc22 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -1857,7 +1857,6 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) break; } - case NI_Vector_ToScalar: case NI_Vector64_ToScalar: case NI_Vector128_ToScalar: { From f139bcffeae3db13ab79baf20c5ece914c41a484 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Tue, 25 Mar 2025 09:44:14 -0700 Subject: [PATCH 4/5] Do not do sve_mov for scalar variant --- src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index d97b16bcf0cc22..4479d8f2d2b1e9 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -2544,7 +2544,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) assert((targetReg == op2Reg) || (targetReg != op1Reg)); assert((targetReg == op2Reg) || (targetReg != op3Reg)); - GetEmitter()->emitIns_Mov(INS_sve_mov, EA_SCALABLE, targetReg, op2Reg, /* canSkip */ true, opt); + GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op2Reg, + /* canSkip */ true); GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op3Reg, opt, INS_SCALABLE_OPTS_NONE); break; From 427e35faf1abcd4c830669f735d8b6f8f8942c1a Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Tue, 25 Mar 2025 12:15:11 -0700 Subject: [PATCH 5/5] jit format fix --- src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 4479d8f2d2b1e9..9bb7a1e4f39356 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -2545,7 +2545,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) assert((targetReg == op2Reg) || (targetReg != op1Reg)); assert((targetReg == op2Reg) || (targetReg != op3Reg)); GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op2Reg, - /* canSkip */ true); + /* canSkip */ true); GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op3Reg, opt, INS_SCALABLE_OPTS_NONE); break;