From 311d0c2af52e77a7fa785b6c75c66a36bce5213f Mon Sep 17 00:00:00 2001 From: Hongqiang Wang Date: Fri, 10 Jul 2026 16:39:16 -0700 Subject: [PATCH] opencl: default the FA c8 cluster width to 16 on X1E too An X1-85 sweep (driver 863, 6 CU; GGML_OPENCL_FA_CL_C in {0,8,16,32}) measured the wider cluster as a real DK128-GQA4 decode win on X1E: +30%/+28% at kv 4096/8192 (95.89->124.66, 97.18->124.49 GFLOPS), peaking at C=16 (C=32 falls back to 106-110 GFLOPS, so this is not thermal drift), with DK64, GQA1, GQA8 and quantized-KV configurations all neutral. X1E was left at the kernel-default width when X2E got 16 because its compiler holds the default width unspilled and wide-C was unmeasured there; the sweep shows the wider cluster wins anyway (fewer position streams per subgroup is the deciding property at DK=128, not just register pressure). --- ggml/src/ggml-opencl/ggml-opencl.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/ggml/src/ggml-opencl/ggml-opencl.cpp b/ggml/src/ggml-opencl/ggml-opencl.cpp index fc0fce0d780a..4d15a6d557d3 100644 --- a/ggml/src/ggml-opencl/ggml-opencl.cpp +++ b/ggml/src/ggml-opencl/ggml-opencl.cpp @@ -4911,8 +4911,13 @@ static bool ggml_opencl_ensure_fa_variant(ggml_backend_opencl_context * backend_ const int x = (e && e[0]) ? atoi(e) : 0; return (x == 8 || x == 16 || x == 32) ? x : 0; // 0 = per-gen default }(); + // X2E needs 16 to keep per-lane o_acc at 128B (the compiler spills the + // kernel-default width); X1E does not spill, but C=16 is still a measured + // +28-30% DK128-GQA4 decode win there (X1-85, kv 4096/8192), neutral on + // DK64 / GQA1 / quant-KV. const int fa_cl_c_gqa4 = fa_cl_c_env ? fa_cl_c_env - : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E ? 16 : 0); + : (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E || + backend_ctx->adreno_gen == ADRENO_GPU_GEN::X1E ? 16 : 0); const std::string opts_cl_c_gqa4 = fa_cl_c_gqa4 ? " -D FA_CL_C=" + std::to_string(fa_cl_c_gqa4) : std::string(); const std::string fa_cl_c_g8_val = std::to_string(fa_cl_c_gqa4 ? fa_cl_c_gqa4 * 2 : 16);