…a76c18 long-prompt result (#364)
* docs: note the engine#315 pin movement in KNOWN-ISSUES.md
The entry cites 26330cc20490 as the pin engine@main ships; main now pins
e44c9d01a4d5 with hrx-system 98d05d94 (#361 reverted in #363). The study's
measurements still describe what ships: 98d05d94 is the same runtime, and
26330cc20490 is an ancestor of e44c9d01a4d5.
* docs: the engine#315 pin note covers #373 and the hrx-system 4ba76c18 long-prompt result
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
---------
Co-authored-by: bong-water-water-bong <bong-water-water-bong@users.noreply.github.com>
Co-authored-by: bong-water-water-bong <bong-water-water-bong@1bit.gg>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Moves
third_party/llama.cppe44c9d01a4d5 -> 0e255d774032 (fork tip after #98, #99 via #100, #100).third_party/hrx-systemstays at 98d05d94: 4ba76c18 returns end-of-text on long prompts (#369). Registry regenerated (hrx 292, npu 7, mapped 292;tools/registry_build.py --check-pinsclean).Verified on strixhalo (performance mode, HRX0 visible via
IREE_HAL_AMDGPU_LIBHSA_PATH, every GPU step under box.lock; logs~/wt/pinverify-0e255d7/):ctest: 25/25 passed.tests/serve_e2e.shhrx and cpu on Qwen3-0.6B: PASS, "Paris.", 32 chunks each.-np 1 --jinja, temperature 0, cache_prompt false): 20/20 answer "7341", 5 completion tokens, same hash on all 20; probe: finish=stop, 0 NaN lines.test-backend-ops -b HRX0twice: 1141/1141 both, Backend HRX0 OK (the HRX: intermittent MUL_MAT f32 m=1 n=1 k=2048 error on common.mul_mat.f32_f32_decode (about 1 in 40 runs at fork tip e44c9d0) #370 flake did not appear).1bit serve --device hrx(one Paris request each, 0 NaN lines): Qwen3-0.6B-NVFP4, Qwen3.8-27B-iMatrix-NVFP4-MTP, qwen38-27b-qat-q2_0, Qwen3-0.6B-emb-iq3_s, Qwen3-0.6B-emb-iq4_nl all answer Paris.CI here builds without HRX; the above is the Strix Halo gate from docs/hrx.md.
🤖 Generated with Claude Code