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Bump gpu-kernels: abaa6bc484d5 (batched MoE decode on our kernels) - #521
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…ur kernels gpu-kernels #25 (pi bw220): llama-server --parallel N batches N sequences into one decode step; the MoE expert steps with 2..8 tokens now dispatch our HIP MoE decode kernels instead of the prompt-shaped WMMA tiles. Qwen3-Coder-30B-A3B aggregate decode (90 W cap, PCM pad): N=2 76.5 -> 95.0-95.6 (+24%), N=4 100.2 -> 119.6-121.7 (+20%), N=8 flat, N=1 untouched (bit-identical single-stream: KLD RMS 0.001%, identical greedy text, test-backend-ops MUL_MAT_ID 132/132, hw-gate ops/kat/placement PASS). Dense models unchanged. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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Moves config/gpu-kernels.config from
4f586caca414toabaa6bc484d5.gpu-kernels #25:
llama-server --parallel Nbatches N sequences into one decode step; the 2..8-token MoE expert steps now run on our HIP MoE decode kernels instead of prompt-shaped WMMA tiles (single-token decode and prompts untouched;GGML_HRX_DISABLE_DISPATCH=hip.moe_tokensturns the pair off).Evidence (strixhalo, 90 W cap, PCM pad): Qwen3-Coder-30B-A3B aggregate decode N=2 76.5 -> 95.0-95.6 tok/s (+24%), N=4 100.2 -> 119.6-121.7 (+20%), N=8 flat; dense models unchanged; N=1 bit-identical (KLD RMS 0.001%, identical greedy text on 3 prompts); test-backend-ops MUL_MAT_ID 132/132 vs CPU; hw-gate ops 695/695, kat 9/9, placement all on HRX.
Merge by hand after hw_gate passes (auto-merge off).
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