Name		Name	Last commit message	Last commit date
README.md		README.md
alu.v		alu.v
alu_mux.v		alu_mux.v
control_unit.v		control_unit.v
cpu.v		cpu.v
data_path.v		data_path.v
ir.v		ir.v
pc.v		pc.v
reg_group.v		reg_group.v
register.v		register.v
state_transition.v		state_transition.v
tb_cpu.txt		tb_cpu.txt
tb_cpu.v		tb_cpu.v

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DCD_LAB

Course project for a CPU Design

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Course project for a CPU Design

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