[Yxmura]

Round 2: IQ1_S made first-class across the pipeline, plus a PM-driven PCIe share.

What

• IQ1_S (type 19) on the GPU and on AVX-2. Unsloth UD-IQ1_S packs did not run at all before: dq_iq1_s, vec_dot_iq1_s_q8_1, Fmt<19>, Split<19>, the grouped kernels, the reader geometry, and the AVX-2 row_dot_iq1s/row_dot_iq1m.
• IQ1_S + IQ1_M on 512-bit lanes. iq512_supported listed neither, and native_expert.cpp only takes the AVX-2 kernel off an AVX-512 CPU, so AVX-512 CPUs ran both through ggml-cpu single-token — slower than an AVX-2 CPU. No EVEX vpsignb, so the grid sign is vpabsb + a masked subtract.
• IQ1_S on the MMQ prompt path. IQ1_S was absent from _strata_mmq_types, mmq::supported() and the dispatch switch, so UD-IQ1_S prefill fell back to per-expert dequant→FP16. Added; the mmq-instance-iq1_s.cu already exists in the pinned ggml.
• The PCIe share measures itself (serve). --pcie-frac was the link probe alone (capped 0.55); the best share also depends on the CPU/GPU and runs both ways. A --serve sweeps the probed share, 0 and 1.0 over its first verify windows, keeps the lowest (CPU pool + GPU wait) per routed expert entry, and holds it. --pcie-frac <value> pins; --pcie-frac auto for the CLI.

Measured

Radeon PRO W7800 (gfx1100, ROCm 7.13), Ryzen 7 3800X, 30 GiB RAM; UD-IQ1_S (67.5 GiB); 600-token prompt, MTP.

	before	after
UD-IQ1_S loads/answers	no	yes
decode (this box)	26.5 tok/s (probed share)	40.2 → 75.3 tok/s (measured, held)
prefill	169.7 tok/s	326.8 tok/s (+93%: +16% the other formats, +66% from IQ1_S MMQ alone)
AVX-512 CPU, IQ1_S/IQ1_M gate/up	ggml-cpu single-token	multi-token AVX-512

The share runs both ways, which is why it is measured: here the GPU taking every miss is fastest, while in the RDNA2 x8 bench --pcie-frac 0 beat the probed 0.39.

Validation

• HIP gfx1100 + full strata; iq_parity (IQ1_S/IQ1_M dequant rel 0.00e+00), iq_multi_parity, native_expert_parity (IQ1_S 3.1e-08, IQ1_M 4.1e-08 vs ggml-cpu), native_grouped_parity — 0 failures.
• AVX-512 path under Intel SDE -spr (this Zen 2 cannot run it): rel ~1e-07 vs ggml-cpu, width-invariant, 0 failures.
• hip_prefill_mmq_parity extended with a synthetic IQ1_S case: rel_l2 0.0038 (limit 0.04), max_abs/ref_rms 0.0145, 0 zero rows.

[Yxmura]

Merged main in to clear the conflict (was CONFLICTING).

The conflict: main moved iq256_supported() / iq512_supported() out of iq_avx2.cpp / iq_avx512.cpp into native_expert.cpp (an ISA-free file, per #795). This branch had edited those functions in place to add IQ1_S (type 19) and type 29.

Resolution: take main's deletion in the two ISA files, and port the branch's added types into the relocated functions in native_expert.cpp:

• iq512_supported: 16|17|18|19|21|22|29
• iq256_supported: 16|17|18|19|21|22|23|29

Validated (ROCM 7.13, gfx1100, pinned ggml 3cf03257):

• iq_parity, iq_multi_parity, native_grouped_parity: pass
• hip_prefill_mmq_parity: pass, including the new synthetic-IQ1_S-GU case (type=19, rel_l2=0.00377, 0 zero rows)
• full strata engine target builds

No other conflicts; the branch now sits on current main.

[Yxmura]

Merged main (0.1.42) again; the branch is clean against it.

• iq_avx2.cpp / iq_avx512.cpp / native_expert.cpp: the earlier resolution carried over, the predicates live in native_expert.cpp with IQ1_S (19) and IQ1_M (29).
• generate.cpp: main's PcieAuto and this branch's --pcie-frac auto sweep both measure the share, so both stay, one driver at a time. An explicit --pcie-frac auto picks the sweep, PcieAuto otherwise when it is armed.

Built the merged tree (strata, HIP gfx1100) and ctest -R 'iq_parity|iq_multi_parity|native_grouped_parity': 4/4.

[Niko1221]

Thanks. The PR bundles three things: IQ1_S support, IQ1_S on the MMQ prefill path and a measured PCIe share that changes the default. We cannot validate IQ1_S here (no UD-IQ1_S pack and no gfx1100 card), and the PCIe part overlaps the share refinement already in the engine, so we are not taking it as a speed change. A PR with only the IQ1_S format support (kernels + reader + parity tests), rebased on the current main, is something we could review separately.

[Niko1221]

Thanks for the pull request.

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