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Maddoxkkm
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What the release brought for this box (Niko1221#1709 Windows HIP VRAM floor, the HIP stream-capture fix, the Linux-only PCIe telemetry), the merge table with what was kept and why Niko1221#1439/Niko1221#1841/Niko1221#1656 went, the measurements (0.1.42+local +5.6% at 16K; the four new PRs +4.4% on top), and the ranked shortlist for the next cycle (Niko1221#1297 bisect, Niko1221#1909, Niko1221#1324, Niko1221#1167, Niko1221#1298/Niko1221#1151) with the gfx1100 reading list.
Maddoxkkm
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Maddoxkkm
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…10.9% Six PRs merged individually (Niko1221#1297 Niko1221#1909 Niko1221#1324 Niko1221#1167 Niko1221#1298 Niko1221#1151), none of which changes the default path (the arms are opt-in and Niko1221#1297 needs a tuning table). Reading the issue tracker produced the real win: issue Niko1221#1549 documents ring_default_slots() sizing the staging ring at 384 (1024 for a fused ring) when g_pinned_share >= 0.9, and our STRATA_PREFILL_RING=96 override - left from tuning against a smaller budget - was costing 16.5% at 4K and 10.9% at 16K. The override is now gone, so the engine's own rule applies. Measured, with the LRU left off (it buys prefill but eats the resident budget: 11.9 -> 9.1 GiB).
Owner
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Thanks. This is a correctness fix for the AMD layouts rather than a speed change; our CUDA launches size the grid for every group so they were not affected. We will look at it with the gfx906 changes and keep your authorship. |
Owner
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Thanks for the pull request. We're resetting the tracker for 0.2.0-beta. There are more than 1,300 open issues and pull requests, too many for us to review properly, so we're closing everything that isn't being worked on right now. Closed here does not mean rejected. To reopen it takes about two minutes:
The rules are in CONTRIBUTING.md. |
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Closes #1908.
Summary
When expert groups outnumber launch block rows, mode 8's fused gate/up and modes 7/8's LDS down kernels skip later groups. Stride the group index by
gridDim.yin both kernels.What changed
Add a model-free regression to
native_grouped_parity: 11 groups, varied entry counts, scattered outputs, nonzero entry offsets, and block-row counts 1/3/8. Check mode 7's down pass and mode 8's complete pass across five gate/up formats and two down formats. No launch defaults or arithmetic changes.Validation
MSVC/CUDA 12.4 build for
sm60;sm75. On RTX 2080 Ti and P100, all 120 new comparisons per GPU fail before the fix and pass afterward; existing default-path checks remain bitwise equal. Targeted CTest and full CUDA integration build pass.Draft pending the affected gfx906 HIP build; no AMD runtime result claimed.