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Rebased onto #357's fix (b26904d), and the same fix for this PR's parameter: 🤖 Generated with Claude Code |
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Rebased on 0.1.32 (c499bd1), no conflicts. Checked on 0.1.32: IQ2_XS (ISTA), RTX 5090, a fixed Still stacked on #357. 🤖 Generated with Claude Code |
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#357 is in 0.1.38, so this part can stand alone now: please rebase it on 0.1.38 as one commit. Because it changes the order of registration and writes (the corruption you hit under WDDM), include the |
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I rebased this onto 0.1.38 as one commit (e121ee3). Part 1 and the header fix came in with #357, so the commit holds only the deferred registration and Checksums, old order against new, measured on 0.1.38.
The times are one start each with the files in the file cache (128 GB), run one after another. So they show the direction, not a measured gain. With 4 KB pages the deferred order is faster every time (2.3-3.6 s); with large pages it makes no difference, as before. |
…eaders (Windows; part 2 of #285) 0.1.31 registers the whole arena with CUDA before the first byte is read. With 4 KB pages, which every account without the Lock Pages privilege gets, that registration is ~1.5 s of the start that nothing hides (IQ2_XS: 33 GiB). - PinnedArena(bytes, bounds, Deferred) reserves only. register_slices() registers the per-layer slices in order on a thread and publishes how many are done. - Every reader (load_experts_gguf buffered and unbuffered, load_experts_ranges, load_experts_direct) writes layer L only once slices L and L+1 are registered. Writing a page while cudaHostRegister runs on it corrupted the arena under WDDM, even on large pages. A layer boundary inside a page puts that page in both registrations, so the next slice must be done too (page-aligned in effect, without moving the slice bounds an expert must not straddle). - A slice CUDA refuses ends the registration, and the rest is locked resident as in the sliced fallback. - Only where the whole arena would be registered anyway: no cap (STRATA_ARENA_PIN_GIB, multi-GPU under WDDM) and no shared arena file. Linux keeps #253's whole-arena pin. STRATA_DEFERRED_REGISTER=0 restores the old order. - STRATA_VERIFY_ARENA=1 prints the loaded arena's FNV-1a checksum (tests). Checksums: the same with the old order and the deferred one, 4 KB and large pages, the GGUF in place and experts.bin (IQ2_XS; 13 deferred loads). IQ2_XS without experts.bin, RTX 5090, 128 GB. Each cell is the time until the arena is loaded / until a 16-token answer is done. Cold: the files pushed out of the file cache first. Two to three runs each: | | cold | restart | |---|---|---| | 4 KB pages (STRATA_NO_LARGEPAGES=1), 0.1.31 | 12.4-13.0 / 16.3-16.8 s | 7.8-8.5 / 10.9-11.7 s | | 4 KB pages, parts 1+2 | 11.1-11.5 / 14.9-15.4 s | 5.5-5.7 / 8.5-8.9 s | | large pages, 0.1.31 | 17.6-18.7 / 21.1-22.4 s | 4.6-5.1 / 7.0-7.6 s | | large pages, parts 1+2 | 17.6-19.9 / 21.3-23.6 s | 4.1-4.5 / 6.7-7.1 s | The cold spread with large pages comes from the drive: the same build gave 17.6 and 19.9 s with the deferred registration and the cache probe switched off as well. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01VZy1yKaDDiA8a7svdwaHio
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Rebased onto 0.1.39 (59d97b3), still one commit. The conflict was in Checked on 0.1.39 (RTX 5090, IQ2_XS, GGUF read in place, 4 KB pages with
That is the same checksum as the 16 runs on 0.1.38. |
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Reopened as #1039, the same branch and commit. GitHub closed this one when my fork was made private by mistake, which took it out of the fork network. |
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Merged in 0.1.40, as opt-in: on Windows the expert arena is registered per layer on a thread ahead of the readers (STRATA_DEFERRED_REGISTER=1; STRATA_VERIFY_ARENA=1 prints the checksum). It is off by default because it cost about 8% decode on Windows here. |
…early (Niko1221#285's part 3, kept here) Upstream got Niko1221#357/Niko1221#358 only: on IQ2_XS part 3 did not move the first decode step. With the NVFP4 pack it does: the 63 GiB arena overlaps the dense weights, the PLE table and the drafter, and the arena is loaded at 6.6-7.4 s instead of 8.0 (the same as 0.1.28-nvfp4.4's 6.7). The first cuBLAS handle is made on a thread meanwhile, so its VRAM is counted before the expert cache is sized - as in 0.1.28-nvfp4.4 (7,221 slots): the 1500 MiB reserve stays 1500. The card check now runs before the arena thread starts, so a build without code for the card stops at once. STRATA_ARENA_SYNC=1 keeps the old order. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01VZy1yKaDDiA8a7svdwaHio
Part 2 of the #285 split. One commit on 0.1.38 (part 1, #357, is in 0.1.38). The start times below were measured on 0.1.31; the checksums on 0.1.38 are in the comments.
0.1.31 registers the whole arena with CUDA before the first byte is read. With 4 KB pages, that registration is ~1.5 s of the start that nothing hides (IQ2_XS: 33 GiB). Every account without the Lock Pages privilege gets 4 KB pages.
What changes:
PinnedArena(bytes, bounds, Deferred)only reserves the arena.register_slices()registers the per-layer slices in order on a thread and publishes how many are done.load_experts_gguf(buffered and unbuffered),load_experts_rangesandload_experts_direct.cudaHostRegisterruns on it corrupted the arena under WDDM, even on large pages.STRATA_ARENA_PIN_GIB, multi-GPU under WDDM);STRATA_DEFERRED_REGISTER=0restores the old order.STRATA_VERIFY_ARENA=1prints the loaded arena's FNV-1a checksum (for tests).Checksums match. The old order and the deferred one give the same checksum across:
Start times
Setup:
generateof 16 tokens.128 GB (the file cache can keep the files), two to three runs each:
STRATA_NO_LARGEPAGES=1), 0.1.31The cold spread with large pages comes from the drive: the cache flush reads 142 GB from the same NVMe. A/B runs of this branch with
STRATA_DEFERRED_REGISTER=0(19.9 s) and withSTRATA_UNBUFFERED_LOAD=0(17.6 / 18.8 s) fall inside that same spread.An emulated 64 GB PC (a locked-pages RAM ballast leaves 58 GiB):
With large pages under that memory pressure, the allocation itself takes 6-12 s and varies from run to run. Windows has to gather contiguous 2 MB pages before the first byte is read, hence the wide ranges in both rows.
Part 3 is dropped
I built and measured part 3 too: the arena opened on its own thread beside the dense weights, plus a cuBLAS handle made on a thread. It gave no net gain here:
So it is not part of the split.
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https://claude.ai/code/session_01VZy1yKaDDiA8a7svdwaHio