What is the feature you'd like to have?
Lifting of the BEXTR instruction is currently handled as an intrinsic.
This produces hard to understand HLIL, and could be improved if it was lifted to a bit-shift/mask instead.
Assembly:
00000000 b902010000 mov ecx, 0x102
00000005 c4e270f7c7 bextr eax, edi, ecx
0000000a c3 retn
HLIL:
00000000 uint64_t sub_0(int32_t arg1)
00000005 uint64_t rflags
00000005 int32_t temp0
00000005 temp0, rflags = __bextr_gpr32d_gpr32d_gpr32d(arg1, 0x102)
0000000a return zx.q(temp0)
IDA output:
__int64 __fastcall sub_0(unsigned int a1)
{
return (a1 >> 2) & 1;
}
Is your feature request related to a problem?
Can replicate above assembly by pasting these bytes:
b902010000c4e270f7c7c3
Are any alternative solutions acceptable?
Separating the start/len of the bextr intrinsic into 2 separate arguments (and making intrinsic name shorter) could make it more readable, but bit-shift/mask would be best.
What is the feature you'd like to have?
Lifting of the BEXTR instruction is currently handled as an intrinsic.
This produces hard to understand HLIL, and could be improved if it was lifted to a bit-shift/mask instead.
Assembly:
HLIL:
IDA output:
Is your feature request related to a problem?
Can replicate above assembly by pasting these bytes:
b902010000c4e270f7c7c3Are any alternative solutions acceptable?
Separating the start/len of the bextr intrinsic into 2 separate arguments (and making intrinsic name shorter) could make it more readable, but bit-shift/mask would be best.