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Reuse ashhart#1764's existing kernel, resource records and required symbol bindings for the Qwen dense/MoE and Nemotron ModelOpt port. Keep one six-entry numerical/replacement/control set. Cache the serving choice: TF_CUDA_PROMPT_BF16=0 restores the lane but leaves required symbols bound. The threshold is fixed at 1024 rows. Host ABI and fixture-lifetime checks pass; fresh CUDA contract and checkpoint A/B receipts remain required on this rebased tree. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
Dory packs its unquantized projections in the shared BF16 lane layout and runs prompt chunks through Linear. Opt it into ashhart#1764's existing tile at the fixed 1024-row threshold; TF_CUDA_PROMPT_BF16=0 restores the lane. The required symbols stay bound and decode stays on its existing path. Exercise the actual family projection at the CUDA ABI without a device. Fresh greedy and seeded token equality and a 2K prompt timing on a GB10 remain required. Refs ashhart#1762, ashhart#1764.
Adapt ashhart#1764's staged chain-warp gated norm to Qwen dense and MoE. Retain the old recurrence and post kernels and each BF16 boundary; TF_CUDA_GDN_CHAIN_NORM=0 restores their separate launches. Register byte replacements for rows, state, sums and chunk seams with source controls. Host ABI checks pass; device and compiler gates are pending. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
Adapt ashhart#1764's expert-first grid to Qwen MoE's 16-row router. Retain each original FP32 FMA chain and the row-first kernel; TF_CUDA_MOE_EXPERT_FIRST=0 restores its symbol and launch grid. Add FP64 and byte-replacement contracts, padded/live-row cases and a source row-coupling control. Complete shared contract image routing, keep callback tables static, and compile GDN controls with the production chain so their compiler flags match. Device qualification is pending. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
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Qualification update on Hosted format passed. The No GPU run was cancelled before completion, as was the previous head's run. There has been no subsequent push to supersede this head. The macOS Could a maintainer confirm whether the repeated cancellation is intentional and how to obtain the remaining hosted checks? I have not changed workflow policy or repeatedly retried cancelled runs. The outstanding checks remain explicitly unchecked. |
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The complete strict CUDA run is now retained in the receipt, including its full text output and binary identity: The numerical gates and every planted control passed their intended checks; six existing NaN findings reproduce. All four new function records pass live sm_120 checks, and all 20 new function/SM records are current in the five-SM asset audit. The remaining failure is 188 registry problems plus 154 live record/device mismatches. The separate parent/candidate five-SM audits both exit 1 with 637 problems and identical diagnostic multisets; the comparison retains those diagnostics. The parent's full/live-only run was not run, so this is not presented as a matching parent live SUMMARY or a clean qualification. Could the maintainer advise the appropriate catalog-resolution scope for these existing records? The PR stays draft. Native serving measurements have resumed, with performance, lifecycle, cold-prefill and existing-format receipts still pending. |
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Thank you, @akol1. This is careful work: the dense BF16 path keeps every existing checkpoint on main's code, the |
(cherry picked from commit d8f5efb)
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Your callback fix ( |
Load the dense Qwen3.5-27B checkpoint from its stored BF16 safetensors and serve per-token prompt logprobs from the rows the prompt path scores. Dense attention and MoE projections keep the checkpoint's BF16 weights and activations; FP32 sums and the stored GDN scales are unchanged, and no tolerance moves. Score the served rows locally: `prompt_logprobs` follows `/v1/completions`, `top` accepts 0/1/20, the first entry stays null, and an unknown `top` or an input id at the vocabulary sentinel is a 400. The head accumulates in FP32 and takes its logsumexp over the full vocabulary. Add an independent FP32 head over the same captured BF16 normalized rows, with its own build, a FP64 dot/logsumexp tool and planted controls, so a score can be checked without trusting the production head. Register the new function/SM and record identities with byte replacements; existing declarations and tolerances stay as they are. The CUDA contract still fails 342 launch limits, so this is qualification input, not a passed contract. Refs ashhart#1762, ashhart#2020.
…erence The receipt tree carried 3.26 MB of per-request dumps and the complete CUDA contract log beside the summaries. Remove the per-request dumps, the two per-request concurrency bodies and the cold replay bodies; asset.json pins the sha256 and byte count of every removed file, and of the transformers payload and run log kept out of the tree with them, so the tracked receipts stay auditable against what was removed. The removed files themselves stay with the author and are not published. Add tools/zig/qwen35_transformers_reference.py, which runs the pinned checkpoint on CPU in two arms, stored BF16 and every decoder layer's stored parameters and buffers promoted to FP32, and transformers-comparison.json, which compares the served prompt scores against that forward and adds the tables to the receipt. The transformers arm's own BF16-to-FP32 distance bounds the comparison: 18/18 rows stay inside their bound, the worst tracked native-to-transformers difference is 0.830 on one prompt row at position 255, the other 17 rows are at or under 0.018, and 408/415 argmax rows agree. The BF16 arm's hidden states are bitwise equal to a plain library forward, and extending a prompt by the served continuation tokens leaves the prompt rows bitwise unchanged. Also name the existing GPU lock and admission guard, with one model process per test machine, in the recipe's serving line, and re-pin the commit ids the topic rewrite changed in the required checksum records. Refs ashhart#1762, ashhart#2020.
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Load the dense Qwen3.5-27B checkpoint from its stored BF16 safetensors and serve per-token prompt logprobs from the rows the prompt path scores. Dense attention and MoE projections keep the checkpoint's BF16 weights and activations; FP32 sums and the stored GDN scales are unchanged, and no tolerance moves. Score the served rows locally: `prompt_logprobs` follows `/v1/completions`, `top` accepts 0/1/20, the first entry stays null, and an unknown `top` or an input id at the vocabulary sentinel is a 400. The head accumulates in FP32 and takes its logsumexp over the full vocabulary. Add an independent FP32 head over the same captured BF16 normalized rows, with its own build, a FP64 dot/logsumexp tool and planted controls, so a score can be checked without trusting the production head. Register the new function/SM and record identities with byte replacements; existing declarations and tolerances stay as they are. The CUDA contract still fails 342 launch limits, so this is qualification input, not a passed contract. Refs ashhart#1762, ashhart#2020.
…erence The receipt tree carried 3.26 MB of per-request dumps and the complete CUDA contract log beside the summaries. Remove the per-request dumps, the two per-request concurrency bodies and the cold replay bodies; asset.json pins the sha256 and byte count of every removed file, and of the transformers payload and run log kept out of the tree with them, so the tracked receipts stay auditable against what was removed. The removed files themselves stay with the author and are not published. Add tools/zig/qwen35_transformers_reference.py, which runs the pinned checkpoint on CPU in two arms, stored BF16 and every decoder layer's stored parameters and buffers promoted to FP32, and transformers-comparison.json, which compares the served prompt scores against that forward and adds the tables to the receipt. The transformers arm's own BF16-to-FP32 distance bounds the comparison: 18/18 rows stay inside their bound, the worst tracked native-to-transformers difference is 0.830 on one prompt row at position 255, the other 17 rows are at or under 0.018, and 408/415 argmax rows agree. The BF16 arm's hidden states are bitwise equal to a plain library forward, and extending a prompt by the served continuation tokens leaves the prompt rows bitwise unchanged. Also name the existing GPU lock and admission guard, with one model process per test machine, in the recipe's serving line, and re-pin the commit ids the topic rewrite changed in the required checksum records. Refs ashhart#1762, ashhart#2020.
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Reuse ashhart#1764's existing kernel, resource records and required symbol bindings for the Qwen dense/MoE and Nemotron ModelOpt port. Keep one six-entry numerical/replacement/control set. Cache the serving choice: TF_CUDA_PROMPT_BF16=0 restores the lane but leaves required symbols bound. The threshold is fixed at 1024 rows. Host ABI and fixture-lifetime checks pass; fresh CUDA contract and checkpoint A/B receipts remain required on this rebased tree. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
Dory packs its unquantized projections in the shared BF16 lane layout and runs prompt chunks through Linear. Opt it into ashhart#1764's existing tile at the fixed 1024-row threshold; TF_CUDA_PROMPT_BF16=0 restores the lane. The required symbols stay bound and decode stays on its existing path. Exercise the actual family projection at the CUDA ABI without a device. Fresh greedy and seeded token equality and a 2K prompt timing on a GB10 remain required. Refs ashhart#1762, ashhart#1764.
Adapt ashhart#1764's staged chain-warp gated norm to Qwen dense and MoE. Retain the old recurrence and post kernels and each BF16 boundary; TF_CUDA_GDN_CHAIN_NORM=0 restores their separate launches. Register byte replacements for rows, state, sums and chunk seams with source controls. Host ABI checks pass; device and compiler gates are pending. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
Adapt ashhart#1764's expert-first grid to Qwen MoE's 16-row router. Retain each original FP32 FMA chain and the row-first kernel; TF_CUDA_MOE_EXPERT_FIRST=0 restores its symbol and launch grid. Add FP64 and byte-replacement contracts, padded/live-row cases and a source row-coupling control. Complete shared contract image routing, keep callback tables static, and compile GDN controls with the production chain so their compiler flags match. Device qualification is pending. Refs ashhart#1762, ashhart#1764. Co-authored-by: Armin <2369138+Arminova@users.noreply.github.com>
Load the dense Qwen3.5-27B checkpoint from its stored BF16 safetensors and serve per-token prompt logprobs from the rows the prompt path scores. Dense attention and MoE projections keep the checkpoint's BF16 weights and activations; FP32 sums and the stored GDN scales are unchanged, and no tolerance moves. Score the served rows locally: `prompt_logprobs` follows `/v1/completions`, `top` accepts 0/1/20, the first entry stays null, and an unknown `top` or an input id at the vocabulary sentinel is a 400. The head accumulates in FP32 and takes its logsumexp over the full vocabulary. Add an independent FP32 head over the same captured BF16 normalized rows, with its own build, a FP64 dot/logsumexp tool and planted controls, so a score can be checked without trusting the production head. Register the new function/SM and record identities with byte replacements; existing declarations and tolerances stay as they are. The CUDA contract still fails 342 launch limits, so this is qualification input, not a passed contract. Refs ashhart#1762, ashhart#2020.
…erence The receipt tree carried 3.26 MB of per-request dumps and the complete CUDA contract log beside the summaries. Remove the per-request dumps, the two per-request concurrency bodies and the cold replay bodies; asset.json pins the sha256 and byte count of every removed file, and of the transformers payload and run log kept out of the tree with them, so the tracked receipts stay auditable against what was removed. The removed files themselves stay with the author and are not published. Add tools/zig/qwen35_transformers_reference.py, which runs the pinned checkpoint on CPU in two arms, stored BF16 and every decoder layer's stored parameters and buffers promoted to FP32, and transformers-comparison.json, which compares the served prompt scores against that forward and adds the tables to the receipt. The transformers arm's own BF16-to-FP32 distance bounds the comparison: 18/18 rows stay inside their bound, the worst tracked native-to-transformers difference is 0.830 on one prompt row at position 255, the other 17 rows are at or under 0.018, and 408/415 argmax rows agree. The BF16 arm's hidden states are bitwise equal to a plain library forward, and extending a prompt by the served continuation tokens leaves the prompt rows bitwise unchanged. Also name the existing GPU lock and admission guard, with one model process per test machine, in the recipe's serving line, and re-pin the commit ids the topic rewrite changed in the required checksum records. Refs ashhart#1762, ashhart#2020.
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Load the dense Qwen3.5-27B checkpoint from its stored BF16 safetensors and serve per-token prompt logprobs from the rows the prompt path scores. Dense attention and MoE projections keep the checkpoint's BF16 weights and activations; FP32 sums and the stored GDN scales are unchanged, and no tolerance moves. Score the served rows locally: `prompt_logprobs` follows `/v1/completions`, `top` accepts 0/1/20, the first entry stays null, and an unknown `top` or an input id at the vocabulary sentinel is a 400. The head accumulates in FP32 and takes its logsumexp over the full vocabulary. Add an independent FP32 head over the same captured BF16 normalized rows, with its own build, a FP64 dot/logsumexp tool and planted controls, so a score can be checked without trusting the production head. Register the new function/SM and record identities with byte replacements; existing declarations and tolerances stay as they are. The CUDA contract still fails 342 launch limits, so this is qualification input, not a passed contract. Refs ashhart#1762, ashhart#2020.
…erence The receipt tree carried 3.26 MB of per-request dumps and the complete CUDA contract log beside the summaries. Remove the per-request dumps, the two per-request concurrency bodies and the cold replay bodies; asset.json pins the sha256 and byte count of every removed file, and of the transformers payload and run log kept out of the tree with them, so the tracked receipts stay auditable against what was removed. The removed files themselves stay with the author and are not published. Add tools/zig/qwen35_transformers_reference.py, which runs the pinned checkpoint on CPU in two arms, stored BF16 and every decoder layer's stored parameters and buffers promoted to FP32, and transformers-comparison.json, which compares the served prompt scores against that forward and adds the tables to the receipt. The transformers arm's own BF16-to-FP32 distance bounds the comparison: 18/18 rows stay inside their bound, the worst tracked native-to-transformers difference is 0.830 on one prompt row at position 255, the other 17 rows are at or under 0.018, and 408/415 argmax rows agree. The BF16 arm's hidden states are bitwise equal to a plain library forward, and extending a prompt by the served continuation tokens leaves the prompt rows bitwise unchanged. Also name the existing GPU lock and admission guard, with one model process per test machine, in the recipe's serving line, and re-pin the commit ids the topic rewrite changed in the required checksum records. Refs ashhart#1762, ashhart#2020.
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Rebased and reworked — head is now Receipts: the per-request dumps and the full contract log are out of the tree. Transformers comparison ( Wording: the recipe line now reads "Use the existing GPU lock and admission guard, with one model process per test machine", matching The four base commits stay only until the base lands; once #1762/#2008 are in I drop them and keep the nine. CI is queued on the new head; I'll report anything that goes red. Refs #1762. |
…dence Keep the original measured source and CI identities after the history rewrite. Link the reviewed evidence assets outside the source branch with immutable hashes. Split the finite Transformers reference into bounded modules without changing its numerical functions. Return failure for the measured BF16-distance counterexamples instead of treating a broader hidden-distance diagnostic as acceptance. Scrub identifying runner metadata in future JSON exports and retain seven verdict/privacy regressions.
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Follow-up on
#2008 remains open, so the four inherited base commits stay pending its landing; this follow-up does not touch native conflict paths or force-push history. Recipe lock wording and the fuller main commit message are retained. Native fidelity, catalog/performance acceptance and post-base qualification remain outstanding; GB10 cells remain with the maintainer as offered. Before changing native arithmetic, please confirm whether the intended acceptance is error relative to the Transformers FP32 arm bounded by its BF16 error, or distance directly to its BF16 arm. Both failing directions are reported explicitly. The previous broadened bound is not presented as satisfying either request. |
Collect actual HTTP selected-token scores with exact row/token coverage and cache-off checks. Report both measured BF16-distance directions without replacing the agreed same-weight FP64 gate with an invented cross-engine threshold. Include the long-prompt FP32 arm and reject incomplete reference evidence.
Fill the four five-SM launch receipts from nvcc 13.0.88. Keep later compiler records pending and test the real registry lookups and limits.
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Readiness work is proceeding on the reconciled candidate The final release-compiler build, complete host checks and full pinned Transformers reference (including the previously missing 4097-token FP32 arm) are running. A finite client now collects actual HTTP prompt scores against both reference arms with exact per-position/token coverage and zero-cache checks. Gate scope is the original agreement: same-weight FP64 prompt/decode worst-row/token evidence, the reduction/control, server integration and unchanged existing formats. As that agreement states, the other-engine tolerance need not pass. We will keep both measured distance directions visible and will not use the broader hidden-distance diagnostic as a substitute. The earlier blanket “fidelity fixes required” status overstated the agreed gate; the missing direct served comparison and 4097-token reference coverage are being completed. ATC overlap coverage is incomplete ( |
Restore the 96 FP32 GDN normalization and decay tensors that Transformers auto-dtype downcasts, and verify their original bytes before either precision arm. Keep repeated runs incomplete until they finish and exclude prose and request identifiers from HTTP evidence. Repair two current-main verification prerequisites: reuse the unchanged canonical loads in the block-32 experts rather than adding primitive copies, and let the compiled-image limits command inspect files without initializing CUDA. No native Qwen arithmetic or precision is changed.
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…ship The four NVCC 13.0 resource tuples match the independently qualified cubins. Resolve their formatting overlap with the upstream records and import its two registry regressions through the compiler-set test module so registry.zig stays within the source limit. Inference code and contract values are unchanged; actual GPU execution provenance remains b168b36.
Keep the three stored-FP32 parameter checks active when torch and safetensors are installed. A host without those reference-only dependencies now reports three explicit skips instead of failing test discovery; missing transitive dependencies still fail.
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Thanks @akol1. The rebase is clean on our side: outside the receipts, the code is line for line what we reviewed, so every existing format still takes main's path. Your MLX 4-bit and NVFP4 runs, 20 of 20 token hashes equal, back that. The receipt tree is down from 52,508 lines to 9,250. We checked the 21 kept-out files' hashes in Two things are left:
When this lands, we'll squash the receipt commits, so the full contract text and dumps added and then removed in this series don't stay in history. The four base commits come out once #1762 and #2008 are in, as you said. The 342-problem limit catalog is ours to clear, and we'll run the GB10 cells on our side. |
Keep source-tree summaries and reproduction inputs, with immutable links and member checksums for complete serving, reference and CUDA evidence. Retain exact producer/binary identities, the failed strict cross-engine comparisons, historical attempts and performance limits. Record the full 559-kernel/367-control pass and zero launch-limit problems on sm_120, with six unchanged known findings; other hardware and production/performance qualification remain outside this experimental scope.
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Completed on
The source receipt keeps summaries and reproduction inputs. Unrun physical chips/backends, multiple ranks and optional paths remain explicit. The maintainer-requested simple per-length report uses every scored position, with no hidden-distance term or extra allowance:
The simple length-level rule fails at all four lengths. Median uses |
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Thanks @akol1, for doing the full comparison and for reporting it straight: all 4,511 positions, the 4,097 seam included, both arms, no extra allowance. The reference script split is clean too, and lean is unchanged on our main. The per-length rule fails at all four lengths. Most clearly at 32 tokens, where the worst served row is 0.0415 from FP32 against the BF16 arm's own 0.0239. At 129 and 4,097 the worst rows sit just above (0.0436 against 0.0426). Your FP64 check shows the head is exact on the rows it's given, so the drift comes from earlier in the BF16 body. Could you run a layer-by-layer comparison on the 32-token fixture against transformers FP32, to find the layer where the served rows first leave the BF16 arm's distance? That tells us whether it's one accumulation we can fix or the format's floor. We'll come back on whether it lands as an experimental format with those numbers stated. One more thing: main's layer-pattern change now conflicts with the BF16 branch in |
What this changes
Adds an experimental dense BF16 Qwen3.5 format and native nonstreamed
/v1/completionsprompt_logprobs, using the existing CUDA lane scheduler. Stored FP32 GDN scales stay FP32; the score head uses BF16 inputs, FP32 sums/output and full-vocabulary normalization. Existing formats retain their generation paths and scoring admission.30e9b87284d4cad99ef6b826d95f5578d6341f63. The credited callback-lifetime fix travels with that parent. Parent history stays until it lands; maintainers rebase at landing.b168b36d0cc3503ae69e8bffcad494574019caf5, pinned-main baseline0d19cc19b5b49a0b4a0188a56b6705bbedae91e4. A public-alias metadata correction preserves the qualified source tree; the later parent merge changes two equivalent resource tables and adds two host-only checks. The optional-dependency test guard and final receipt changes do not alter inference or numerical gates. Earlier execution IDs are retained.pullFilesUnavailable,timeLimit). The scan reports open-branch conflicts with qwen CUDA: streams on pages by default (256 positions, the engine's own too), with the paged prompt and decode at the window path's speed #2011 (Qwen page defaults) and glm cuda: EXL3 mcg experts at any whole-bit width, mixed by projection #2094 (EXL3 prompt/registry additions). The parent receipt overlap is resolved. At landing, preserve the BF16 FP32-scale guard and both registry sets, retain per-compiler measured/pending selection, and remeasure changed images; no integration with all open branches is claimed. This PR is currently mergeable against main.Checks on this head
Head:
8f1202644cfadf12c70bfcdca42e28051b69d10c.zig build test test-kernel-contract test-golden fuzz-cortheon -j8 --summary all, exit 0; 570/570 steps, 3872/3897 executed tests passed, 25 skipped, other results cached. Plain build 30/30 and native/capture build 11/11 passed..textsections are byte-identical across the five compiled SMs.Receipt
Summary and reproduction, compact machine-readable summary, immutable assets and checksums. Full per-request/capture results, exact public arrays, failed/superseded attempts and complete logs are outside the source tree at https://github.com/akol1/TensorFold/tree/164be6e57dae9124893e27d8d1ac8a1be7d03f1c.
One RTX PRO 6000 Blackwell Max-Q workstation GPU, sm_120, rank 1, 96 GB class/300 W; Linux x86_64, driver 615.78.08, Zig 0.17.0, NVCC 13.0.88, native 1.2.2. Host CPU: AMD Ryzen 9 9950X3D, 16 cores/32 logical CPUs. Physical RAM: 128 GB class. Serving quota: four CPUs/32 GiB, HTTP loopback, context 8192/C4/cache0 unless stated otherwise. These quotas do not prove fit on a physical 32 GiB machine. One model process holds the existing GPU lock at a time.
Public
Qwen/Qwen3.5-27B, revisionfc05daec18b0a78c049392ed2e771dde82bdf654; all 11 measured shard hashes/sizes match pinned public LFS bytes and were reverified after serving. No weights or drafter are distributed; new-weight licence n/a. Native binary SHA-256:fa2f415a1b7a6f47a62ee078e7f6de86f3f677d2bf74ffa5c2d273e1ce713a64.UnexpectedTensorrefusal for F16 embeddings; no EXL3 inference is claimed.The maintainer-requested simple per-length report uses every scored position, with no hidden-distance term or extra allowance:
The simple length-level rule fails at all four lengths. Median uses
statistics.medianover all rows of that length. This covers the 415 smaller-fixture positions plus all 4096 scored positions of the 4097-ID seam. The full-precision derived report and reproduction script pin the published input member SHA-256. The stricter row-level counts above remain separate diagnostics.Short cells request 128 output tokens, three measured repetitions; warmups excluded. C1/C4 greedy and temperature-0.7 sampled cells are retained with exact IDs, seeds and request settings. All 60 native measured concurrency requests match solo/plain hashes. Six greedy cross-engine content/reasoning fingerprints match; SGLang full-token-ID equality is unverified. Decode excludes the first token; whole-request throughput includes prefill/makespan; SSE chunks are not GPU kernel timings. No production percentile SLO follows from three repetitions.
Cold rows each use a fresh server, cache0/C1, context N+32, exact archived IDs and eight reply tokens. TTFT starts after readiness; model load is separate, startup warmups precede readiness, and OS/compiler/kernel caches are preserved. SGLang's missing HTTP cache counter remains null and its generic qualifier remains false/exit 1; independent scheduler accounting shows exactly N new and zero cached tokens. Native short cold replies sometimes lack enough SSE chunks for decode rate; those rates stay null. All attempts are retained.
Memory is measured separately from timed requests. Native cache0/C4 process/device peaks are 5.984/54.025 GiB; retained-cache peaks 6.000/54.025 GiB, pinned sampled maximum 0.453 GiB. Through the actual native 64k request, process/device lifetime peaks are 5.992/55.302 GiB. Linux process high-water, sampled counters and cgroup charge have distinct scopes. SGLang per-process peaks are not a summed group peak; its short-run cgroup charge reached about 32 GiB. Unavailable device/pinned allocator peaks remain unmeasured.
Complete CUDA contract
The six known NaN findings are identical to the previous declarations; no known entry was added. The full log preserves their actual failures and every planted control.
The five-SM compiled-resource audit exits 0: 1493 records, zero stale records and zero applicable launch failures, launch controls red. Compile records preserve later-compiler selection; launch geometry, precision and tolerances are unchanged. Registered FP32-scale RMS covers real 128-wide GDN shapes, nonfinite values, repeat/guard checks and a red wrong-dtype control. Its FP16 stress misses by 256x; BF16 output rounding can hide BF16 reduction error, as explicitly reported. Scoring reduction controls remain red.
The initial full-suite attempt stopped before numerical gates because independently compiled H3 held only sm_121. Explicit
-Dsm=80,86,89,120,121corrects that setup; the source and gates are unchanged. Exact byte searches compare all 141 file images: only H3 embedding coverage changes, and the served native binary stays identical. Failed attempt, corrected build, runner SHA-256 and full logs are retained separately.Other physical chips/backends, multiple ranks, FP8 KV and optional grammar/tool paths remain unqualified. Vision, int8 prompt precision and learning are explicitly refused for this text format. GB10 execution remains with the maintainer as offered. Compilation for another SM proves resource coverage, not device execution.
Checklist