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arm64: add T8140 PMU support and bound nested stage-2 TLB flushes - #731
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KVM guests on the MacBook Neo (T8140, Tahiti cores) livelock as soon as two private interrupts are pending while the guest has IRQs masked: the vCPU takes the vGIC maintenance interrupt on every entry and never retires an instruction. This is the T6040 problem again: the Tahiti MIDRs are missing from apple_broken_seis_cpus, so kvm_patch_ich_vtr_el2() leaves vgic_ich_vtr() at its placeholder and KVM uses nr_lr = 1 although ICH_VTR_EL2 reads 0x90580007 (8 LRs, SEIS=1). With one LR, KVM sets ICH_HCR_EL2.UIE and the underflow maintenance interrupt fires the moment the guest is entered. Measured under aura's FEAT_NV2 monitor: at every exit of a 2-vCPU guest the hardware reported ICH_MISR_EL2.U with ICH_HCR_EL2 = 0x449b and only LR0 in use (alternately vINTID 27 and SGI 1). Assisted-by: Claude Opus 5.5
Expose the verified cycle and instruction counters through one PMU instance spanning both Tahiti clusters. Keep unknown programmable events rejected while enabling KVM-backed perf migration across P and E cores. Include the T8140 PMU DT binding and IMPDEF PMUv3 capability. Assisted-by: GPT-6.1 Sol
Track the actual valid leaf span cleared by a stage-2 unmap and flush only that range after the walk. Sparse or empty unmaps no longer invalidate the caller's full IPA range, while table retirement keeps its immediate TTL_UNKNOWN flush. Assisted-by: GPT-6.1 Sol
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This series adds the verified fixed cycle/instruction PMU interface for Apple T8140/Tahiti across both CPU clusters and bounds deferred stage-2 TLB invalidation to leaves actually cleared by each unmap walk.
Validation on MacBook Neo J700:
The pressure workload is synthetic compaction and does not establish that the earlier ISO-download slowdown is solved. EFI runtime-service paging faults during diskless poweroff and Windows emulated-TPM errors remain open.