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Merge aurora-wip batch 2 (fleet14c to fleet14f, b359258c) into integration/aurora - #873
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Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the legacy open firmware serialized while moving program storage and completion ownership into tagged frame slots. Leave Borage activation dependent on the register and completion facts absent from the clean specification. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Add deterministic host tests against production helpers and KUnit coverage of slot reuse, ordered retirement, watchdog wrap, inbox retry, command builders and completion parsing. Track the unproved Borage fields explicitly and preserve session generations over firmware reboot. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Remove contexts from the scheduling list before releasing their m2m state, reject already-scheduled jobs during teardown, and keep Apple fp pointers absent on the open backend. Preserve tagged slots over inbox-full retries and avoid periodic watchdog wakeups when only submitted frames remain. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep the CODECS trailer intersection with the SoC capability table when selecting the open backend. Bound firmware copies by the mapped code resource. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Only the H.264 compatibility builder explicitly completes held slice requests during preparation. Continue submitting legacy HEVC requests that retain their capture buffer. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…ation Prevent queued contexts from observing the same free capacity. Run preparation on a context work item because m2m try_schedule can invoke device_run synchronously while the queue mutex is held. Drain that work before freeing the context. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep power through slot retirement and context drains, restore firmware before retrying reserved frames, and defer DMA releases while the DART is inactive. Re-enable a retained Apple MCPU image before mailbox link setup, without uploading it again. Pause and drain the queue for system sleep and final teardown. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Request the mailbox IRQ without automatic enable, open it only after successful firmware boot, and synchronize and close it after backend suspend. Close the host IRQ on teardown even if the final PM transition fails. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Map only DT-declared PIODMA and SRAM resources and replay the shifted SRAM base before every open CM3 boot. Keep reset, empty-domain attach/detach and firmware reboot ordered; refuse to reboot if the DMA domain cannot be restored. Keep host IRQs closed until old slots are invalidated. Add synthetic-RAM boot replay and recovery-gating KUnit coverage. Queued PIODMA use still requires the DT to describe the DMA stream as well as decode. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Replay PIODMA setup in the common boot dispatcher so queued open transports inherit it even with their own mailbox boot implementation. Keep firmware generation handling and initial-only backend fallback in the same dispatcher, and test the real open boot path through it. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Brings in the frame-queue core (avd/rewrite-core) and its runtime and system PM, PIODMA replay and DART recovery (avd/power-idle). Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Each frame in VP to PP flight owns one hardware instruction FIFO, named by EXEC bits 7:4. The hardware has 15 of them on v3 and later tier 1 parts and 7 on T8103 and T8140, so the 16-slot queue must not keep more frames in flight than the variant has FIFOs. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
T6040 decodes HEVC with the v5 header. Add HEVC to its capabilities but keep it hidden unless the loaded open firmware lists h265 in its CODECS trailer, so older firmware without the trailer behaves as before. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
When the VP instruction queue is at least half full the open transport slept a fixed 500-650 us (100-150 us on parts with v5 pacing) before the next segment. Poll the queue level every 10 us instead and continue as soon as it drops below half, keeping the old sleep as the upper bound. The submission order and queue thresholds do not change. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The open transport writes every instruction word to the VP FIFO register from the CPU, sleeps while the FIFO is half full, and kicks the PP from the VP-done interrupt thread, one frame at a time. avd-fw queue ABI 2 moves all of that into the CM3. The host streams each frame program into a word ring in CM3 SRAM, posts a 64-byte descriptor and rings mailbox 0; the firmware feeds the VP FIFO, writes the PP kick (plus one continuation kick per extra segment for HEVC, VP9 and AV1) when the VP is done, and posts a tagged completion on mailbox 1. No PIODMA is used, so the second DART stream that the current device trees lack is not needed. The transport is chosen after every firmware boot from the image info block: ABI 2 with the SRAM ring, and an SRAM aperture matching the node. Anything else keeps the legacy transport. Each frame in flight gets its own instruction FIFO (the slot index), and the queue keeps at most the FIFO count in flight. Frames of one context stay serialized by the queue core, so different streams overlap; within a stream the gain is the removed CPU word writes, pacing sleeps and interrupt round trip. T6040 now loads avd-fw-v5-t2, whose SRAM aperture matches the node, and falls back to v5-t1 when that image is not installed. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
CM3 SRAM keeps its contents across a firmware reload. After an ABI 2 image ran, a later boot of an older image would still show the queue info magic and the driver would pick the queued transport for firmware that does not speak it. Clear the magic before every open-firmware boot so only an image that publishes it again selects queue mode. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
With the firmware chaining VP to PP, the VP of picture N+1 can run while the PP of picture N is still busy, but the legacy H.264 builder kept one set of scratch buffers, one VP to PP instruction FIFO and one slice table per context, and the queue core held the m2m scheduler until a picture retired. Give H.264 two banks of everything the hardware touches while decoding a picture (instruction FIFO, pipe state, above, loop-filter and MV row buffers) and of the slice copies. A new picture takes a free bank and records it in its CAPTURE buffer; retirement frees that bank. Pictures whose last slice never arrived restart in their own bank. The legacy transport keeps one bank, so nothing changes there. The queue core now lets a legacy codec context hold as many pictures as it has banks, carries each frame's FIFO address to the transport, and only keeps the m2m scheduler for slices that hold their CAPTURE buffer, so the next picture is prepared while the previous one decodes. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
… the queue image HEVC gets the same two-bank treatment as H.264 on the queued transport: the VP to PP instruction FIFO, pipe state and all row/column scratch exist once per bank, a picture records its bank in its CAPTURE buffer, and a new done hook frees it at retirement. The VP of picture N+1 then overlaps the PP of picture N. The legacy transport keeps one bank. The per-buffer bank field is now shared by both codecs. Codecs a variant holds back until a newer firmware (fw_caps_required, T6040 HEVC) are now also enabled when the loaded image runs the queue ABI and lists the codec in its info-block codec mask, not only through a CODECS trailer. Falling back to the legacy transport restores the trailer-derived set. Both the transport choice and the codec list come from what the image reports at boot, and clients enumerate formats and size their contexts before a first decode would power the decoder up, so boot the firmware once at probe and let it autosuspend. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
avd_frame gained a DMA address for its instruction FIFO, and the host build of the queue test has no dma_addr_t. Define it in the host shim. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…eue_mutex The threaded interrupt handler takes queue_mutex before it touches the decoder. Queue reset runs from the queue worker with queue_mutex held, and its recovery called disable_irq(), which waits for that handler thread. When an interrupt arrived around a frame timeout, the handler blocked on queue_mutex and the reset blocked on the handler: the worker and the IRQ thread deadlocked with the mutex held. Runtime suspend had a similar cycle with a submission waiting for it under queue_mutex. Close hardware access with a spinlock instead: the handler runs the backend's interrupt code only under irq_lock, with hw_on set and the interrupt generation it sampled before taking queue_mutex unchanged. Turning the IRQ off clears hw_on and bumps the generation under that lock, so an access in progress finishes first and a handler woken by an older firmware instance leaves the hardware alone, and then uses disable_irq_nosync(). Device removal, which holds no queue_mutex, still synchronizes with the handler. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The old driver kicked the PP for every VP DONE message of the open firmware. The legacy shim in the frame queue dropped a VP DONE that came in while no frame was in flight. That happens when a surplus PP DONE of a multi-kick picture completed the next frame early: the next frame's VP DONE then found no active frame, its PP was never started, and it timed out. Kick PP for the last submitting context in that case, as before. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Reading MBOX1_RETRIEVE when the mailbox is empty returns the previous message again. On a spurious or early interrupt that is a repeated PP DONE, which completes the next frame before its PP has run. The next PP then never reports done, the frame times out and the decoder is reset. The legacy shim and the queued transport both popped unconditionally. Check the empty flag in MBOX1_STATUS (bit 17) first, give a message that is not readable yet up to 10 us, and otherwise acknowledge and ignore the interrupt. Both transports share the helper. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
A frame timeout on the J616s was followed by the machine going down with nothing in the journal, so nothing showed how far the recovery got. Log every recovery step (stop firmware, reset, DART flush, firmware boot) before it runs, with the DART, runtime PM and IRQ state at the start, refuse and warn once if recovery is ever entered with the decoder powered off, and name the codec, slot state, frames in flight and transport in the timeout message. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
… a loop The Neo hung after a burst of "H0 error" (VP0, the HEVC VP, raising its error interrupt) with "Frame processing timed out!" for every frame: each error reset the decoder (pmgr reset, DART empty-domain flush, firmware reload), the next frame of the same broken stream failed at once, and the resets ran back to back, up to one per millisecond, until the machine stopped. The frame queue inherited the same loop. Bound it at three levels: - A stream that fails three frames in a row in hardware is stopped: its frames complete with an error, without touching the decoder, until streaming is restarted. - Decoder recoveries are at least 20 ms apart. - More than eight recoveries within 10 s put the decoder in a 10 s cool-down in which new frames fail at once. A faulted decoder (failed recovery) no longer blocks the m2m scheduler, which left clients waiting forever: its frames fail at submission, the request controls are completed so the request fd signals, and the next clean power-up clears the fault. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The HEVC builder computes each slice's coded data address and size from GStreamer's layout: slices tile the OUTPUT buffer as whole NALs, bit_size covers the whole NAL and data_byte_offset is the slice data's offset in it. FFmpeg's V4L2 request backend gives data_byte_offset from the start of the buffer and a bit_size of the slice data only. Every slice then got a wrong address and a size short by its header, the VP raised its error interrupt on every frame, and the decoder was reset once per frame. This is the "H0 error" storm the Neo hit in an FFmpeg-based benchmark. When the slices describe a complete, unambiguous absolute layout, rewrite the run's private copy into the equivalent NAL-relative description. The GStreamer layout and anything ambiguous are left untouched. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
avd-inst.h builds every instruction word with FIELD_PREP() but relied on an indirect include. The arm64 build gets it through other headers; the UML KUnit build of the avd tests does not and fails. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
EDR on the J616s panel asked for the peak in one swap and left it there, with the display EDR scale anchored so that PQ 203 met SDR white, a zero brightness limit in every brightness swap, and a jump straight to the peak again after a power off. After a DPMS cycle with HDR content up, the panel then stayed at about a third of its EDR level (GNOME bt2100: backlight 11-13 W before, 3.9 W after), because a direct jump to the peak does not take after a power on. Follow the sequence macOS uses on this panel (captured on the J616s under macOS 27): with applied headroom H, brightness SDR white x H, display EDR 1 / H and, while the frame uses EDR, headroom used H; H moves linear in stops, one step per swap, about 1 s up and 2 s down, with a brightness limit of 1.3 x the brightness in the middle of a ramp and never a zero limit; headroom used drops to 1.0 as soon as EDR ends; after a power off the ramp starts again from 1.0. PQ 100 now lands at SDR white, as on macOS. On the J616s (fleet14b, DCP 26.6.2) a DPMS cycle with GNOME in bt2100 keeps the panel at 8.7 W instead of dropping to 3.9 W. Full-field SDR white draws less after a PQ session until the next display power cycle (6.1 W to 4.2 W at the same brightness); stock fleet14b does the same, so that predates this change and stays open. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The EDR exit ramped H down one step per swap, as macOS does. macOS's compositor keeps presenting until its ramp ends; GNOME on a still desktop may send no further swap, and with headroom used already back at 1.0 a ramp left partway would keep SDR content scaled down. Return H to 1.0 in the swap that ends EDR, which macOS also does for an immediate transition. On the J616s (fleet14b) the GNOME desktop after leaving bt2100 draws the same backlight power with an exit ramp and without one, and a full-field SDR white after EDR settles as on stock. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
drm/apple: EDR on the desktop 26.x panel the way macOS does (PQ highlights at the panel peak)
ANE: H14 program lifetime
The optional tagged VP DONE event is now committed in avd-fw (bf49a31b, queue feature bit 2), so the patch kept under tests/ is redundant. Remove it and name the firmware commit instead. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The CM3 IRQ routing and FIFO EMPTY bit 17 fixes are committed in avd-fw (50d7f869), so the patch kept under tests/ is redundant. Remove it and name the firmware commit instead. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Keep two complete AV1 scratch banks on queued firmware advertising tagged VP DONE. Look ahead at the pending request's frame control and follow its actual primary-reference timestamp. Default CDFs and references outside the in-flight set do not wait for an unrelated picture. The open firmware's VP event does not establish CPU visibility of AV1 hardware-written CDF, segmentation or motion-field tails. Retain PP retirement dependencies for those inputs. When frame-end CDF updates or segmentation-map writes are disabled, copy preparation's immutable input snapshots into the consumer bank instead of reading live CAPTURE storage. Only PP retirement releases the saved picture's bank. Preserve the legacy emitters and tail preparation, add production host flag/ownership tests and a routed AV1 Unicorn overlap test, and document the remaining visibility evidence requirement. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…nputs" This reverts commit 2f9bd00. The AV1 overlap has host and emulator tests but has not run on AV1 hardware (T6040, T8140) yet, and this branch is about to merge with the code that was qualified on the J616s and the M2. The change is kept on avd/rewrite-av1-overlap and comes back once it is bit-exact on hardware. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
media: apple: avd: frame queue, queued open-firmware transport, picture overlap
…d syntax Port the conformance fixes onto the merged frame-queue rewrite. Advertise HOLD_CAPTURE_BUF before CREATE_BUFS probing and replace format features on S_FMT. Intermediate slices retain CAPTURE through the core HOLD API; the last slice still detaches both buffers without completing DMA ownership. Reject SP/SI, FMO, unsupported SPS controls and arbitrary slice order before building instructions. Check order before selecting a bank can discard a held picture. Drop rejected unsubmitted slices and the job table without releasing a submitted bank belonging to another picture. Map sparse DPB indexes to packed reference-header slots and count every VALID header, including inactive entries. Dense legacy programs retain their bytes; sparse reference operands and inactive-entry counts change intentionally. Fold the old host/queue cases into the existing program and dispatch tests, including exact baseline programs, every DPB occupancy map, CREATE_BUFS probing, held/final/error dispatch and production two-bank preparation. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…ictures Port the reference-free intra-header fix onto the banked H.264 builder. Frame-number gaps can evict every real reference, leaving a non-IDR I picture with an empty hardware DPB. Its inter header cannot encode the empty table because the reference count lives in the first entry. Use the existing IDR intra-only header for an I picture with no VALID references. This sets INTRA, clears NOT_IDR and omits the empty reference preamble. Pictures with references retain the existing header on both transports. Extend the rewrite's program test with 32 exact complete-program checks against the pinned legacy IDR path, preserving before/after evidence. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…ut a DRM mode set" This reverts commit 64e23b4. Reselecting the mode on every VRR_ENABLED change blanks an external display for about 5 seconds each time. GNOME turns VRR on when a fullscreen client is scanned out directly and off again when it stops (a cursor move is enough), so on an MSI MPG 325CQRXF a fullscreen browser kept dropping out. Keeping adaptive sync installed and moving only the rate does not work on these processors either: with VRR_ENABLED clear, neither a minimum rate nor a media target rate of 280 Hz kept the display fixed, and an idle desktop ran variable and flickered. Go back to requiring a mode set for a VRR_ENABLED change on the external processors until the way the firmware holds a fixed rate with adaptive sync installed is known. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
media: apple: avd: H.264 slice hold and intra-header fixes on the rewrite
On T8140 the video encoder cluster (VENC-CLSTR-V) has an enable bit in a PMC control word, with a matching status word. The PMP only raises the encoder performance state while the cluster is enabled, and macOS sets the bit, under its PMC lock, whenever the encoder is powered. Describe such bits as child nodes with apple,cluster-bit, in an optional "clusters" register range (control word, then status), and provide each as a power domain: power on sets the bit and waits for its status, power off clears it. The read-modify-write runs under the PMC lock. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
…th its power request A PMP soc-device can have a performance request beside its power request: on T8140 the encoder (soc-device 15, AVE0) asks for its VMAX state in SOC-DEV-DVFS entry 0x198, and the PMP then votes the AVE rail up itself, as it does under macOS. Let a report entry name that entry and level with apple,dvfs. After the PMP acknowledges the power request, write the level with the valid bit in one 64-bit store; before clearing the power request, write level 0. Never read a request entry back after storing it: that read retires the pending PTD update before the PMP handles it, and the request is lost. The T8140 offsets gain the update aperture and the SOC-DEV-DVFS range. The T6030 graph host test harness follows the entry struct. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Add the VENC cluster enable bit to the PMC, a PMP report entry for soc-device 15 (AVE0) under VENC0_SYS and the cluster that requests VMAX in SOC-DEV-DVFS entry 0x198, and hand it to the encoder as its "perf" power domain, held while the encoder is powered. On a Neo one-shot (fleet14c, the same requests made by a test module) 1080p H.264 went from 110 to 165 fps (macOS 178), HEVC 101 to 153 and 4K H.264 30 to 47, with the PMP voting the AVE rail to state 2. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Neo encoder performance request (1080p H.264 110 to 165 fps)
With GNOME in HDR on the J616s panel, the shutdown splash came out far too bright. Connector properties outlive the client that set them, so Plymouth inherited HDR_OUTPUT_METADATA with the PQ EOTF and the BT.2020 colorspace, and its SDR frames were shown as PQ near the panel's peak. When a file that was DRM master closes and no other client has taken master, take every output it left in HDR back to SDR with the same commit an HDR-off from the compositor would make: no HDR metadata and the default colorspace. A compositor that only drops master for a VT switch keeps its state, since it does not send it again when it comes back. On the J616s panel at brightness 300, SDR white after a PQ client exits now draws 4.4 W (SDR white 6.0 W, the PQ client 14.9 W). Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
A desktop 26.x panel shows PQ as EDR: PQ 100 cd/m² lands on the white the backlight sets, and brighter levels use the headroom above it, up to the panel's peak. The backlight stays in effect while it decodes PQ. macOS uses the panel the same way. Compositors can't tell this from the panel EDID or any existing connector property. They take PQ as absolute, with the reference white at 203 cd/m², and mutter also drives the backlight to its maximum in BT.2100 mode because it can't tell whether the backlight still works. On this panel that made the HDR desktop about twice as bright as SDR, or more. Attach an immutable PQ_REFERENCE_LUMINANCE range property, in cd/m², to the panel connector of a desktop 26.x DCP. Its presence says the backlight still applies in PQ, and its value is the PQ level that shows at the white the backlight sets. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
When HDR ends on a live desktop 26.x external link, the driver only set the SDR colour mode and relied on the link to drop the Dynamic Range and Mastering InfoFrame. macOS first stops that InfoFrame with DCPAV selector 0x14 (stopInfoFrame, type 0x87) on dcpav-service-epic, requires the stop to succeed, and only then sets the SDR colour mode. It never sends an empty metadata block. Do the same. Track whether the firmware took a metadata block, so that the link carries the InfoFrame. When a mode set leaves PQ on such a link, send the 0x14 stop first. The stop message is a fixed 0x80 bytes: the DCPAV header, a 32-byte InfoFrame at 0x40 whose type byte (0x87) selects the slot to clear, the link source at 0x60 and the DCP status at 0x70. A failed stop is reported, and the mode set goes ahead. A link set up again (power off, new service) carries no InfoFrame, so nothing is stopped there. The host selftest checks the stop message byte for byte against an independent encoding, and checks its reply status offset. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
Port multi-VP selection onto the current queued transport without losing its SRAM word stores, IRQ/mailbox fixes, saved frame FIFO or tagged VP DONE. Negotiate an optional AVM2 codec pool record and rotate submissions through its VP masks. Old firmware retains the k4m selector and two picture banks. Size H.264 and HEVC banks for the advertised VPs plus ordered PP ownership, limited by the available FIFOs. Their VP work uses private slice state; firmware still starts PP in submission order. Keep VP9 probability producer barriers and AV1's single-picture path intact. Exercise negotiation, fallback, rotation/retry, production picture banks and routed single-stream programs, including reverse VP completion order. Document the inferred T6040 pool and the remaining silicon qualification. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
The production picture-bank query accepts a const device. Match that signature in the host boundary so its HEVC bank lifetime checks compile with warnings treated as errors. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
drm/apple: Revert the VRR mode reselect on desktop 26.x externals
…into lane1/md # Conflicts: # drivers/gpu/drm/apple/iomfb.c
drm/apple: GNOME HDR on the J616s (PQ reference white, SDR on compositor exit, InfoFrame stop)
media: apple: avd: enable queued multi-VP decoding on aurora-wip
…tion/aurora Bring integration/aurora up to aurora-wip b359258, the source of 7.3.0-aurora-fleet14f, promoted on the M1 Pro, M2, Neo and J616s on 2026-11-01 and 11-02. The range also covers the fleet14c, fleet14d and fleet14e sources (f41ac3d, 4759557, 757fc07), each booted on hardware. It adds #773, #776, #777, #737, #713, #785, #786, #788, #789 and #787. No conflicts. Assisted-by: LLM Signed-off-by: Ryan Murray <ryan@aurorasilicon.org>
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Batch 2 of 6 bringing integration/aurora up to aurora-wip. It's a merge commit, with no rebase and no rewrite.
Range
aurora-wip up to b359258 (fleet14f). The range also covers the fleet14c (f41ac3d), fleet14d (4759557) and fleet14e (757fc07) sources.
PRs: #773 AVE/AVD perf votes, #776 external VRR, #777 panel EDR, #737 ANE H14 fw alloc lifetime, #713 AVD rewrite, #785 H.264 conformance, #786 Neo AVE perf request, #788 revert of #776's reselect, #789 GNOME HDR on the J616s, #787 AVD multi-VP.
No conflicts. The merged tree is the aurora-wip boundary tree plus the #858 and #860 patch content that integration/aurora already had (as #855 and #856). Only drivers/usb/typec and the aurora-sep files differ from the booted fleet source.
Hardware evidence
Source: aurora-ctl/reports/fleet14-20261101/RESULTS.md
Gates on this merge tree (buildbox, fleet recipe: canonical Fedora asahi base + asahi.config)
🤖 Generated with Claude Code