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fix(base): preserve negative zero in F32.round #1613

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Merged
Lorenzobattistela merged 1 commit into from
Oct 16, 2026
Merged

fix(base): preserve negative zero in F32.round #1613

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11 changes: 10 additions & 1 deletion bend2/base.bend
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Original file line number Diff line number Diff line change
Expand Up @@ -1863,11 +1863,20 @@ def F32.hypot(a: F32, b: F32) -> F32:
+q = F32.mul(y, s)
F32.mul(F32.sqrt(F32.add(F32.mul(p, p), F32.mul(q, q))), u)

# A rounded zero keeps the input sign, including at the negative half.
def F32.round.zero(a: F32, r: F32, zero: Bool) -> F32:
match zero:
case True{}:
F32.mul(a, 0.0)
case False{}:
r

def F32.round(a: F32) -> F32:
match a:
case F32{+x}:
+f = F32.floor(F32{x})
F32.add(f, Bool.pick(F32, F32.is_ge(F32.sub(F32{x}, f), 0.5), 1.0, 0.0))
+r = F32.add(f, Bool.pick(F32, F32.is_ge(F32.sub(F32{x}, f), 0.5), 1.0, 0.0))
F32.round.zero(F32{x}, r, F32.is_eq(r, 0.0))

def F32.pi() -> F32:
3.14159265
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13 changes: 13 additions & 0 deletions tests/base/f32_round_zero.bend
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Original file line number Diff line number Diff line change
@@ -0,0 +1,13 @@
import Base

def main() -> IO(Unit):
do IO<Unit>:
IO.print(U32.show(F32.bits(F32.round(F32.neg(0.0)))))
IO.print(Bool.show(F32.is_eq(F32.div(1.0, F32.round(F32.neg(0.1))), F32.div(F32.neg(1.0), 0.0))))
IO.print(U32.show(F32.bits(F32.round(F32.neg(0.5)))))
IO.print(Bool.show(F32.is_eq(F32.round(F32.neg(0.5000000596046448)), F32.neg(1.0))))

#|2147483648
#|True
#|2147483648
#|True