Symptom
Unit Tests (CI, ubuntu) failed once on PR #1588 head db08a16b (run 33748523789, 2026-09-03), on a docs-only diff (two lines of codev/resources/arch.md prose; zero source paths touched). Same suite passed on the previous head 91f412be with identical source. 1 failed / 5370 passed:
FAIL src/commands/consult/__tests__/agy-auth-cache.test.ts
> gemini lane burst behaviour (#1077 regression)
> re-probes after the unauth TTL lapses, recovering once the user signs in
AssertionError: expected null to be 'unauth' // agy-auth-cache.test.ts:325
Root cause (from the test source, not speculation)
The test pins CODEV_AGY_AUTH_CACHE_TTL_UNAUTH_MS = '50' and then asserts the pre-lapse state through the TTL-checking reader:
process.env.CODEV_AGY_AUTH_CACHE_TTL_UNAUTH_MS = '50';
...
await runLane(1); // records 'unauth' internally
expect(checkCachedAgyAuth(fakeAgy)).toBe('unauth'); // line 325 — races the 50ms TTL
Any >50ms delay between the cache write inside runLane(1) and line 325 (GC pause, loaded runner, coverage instrumentation) lapses the verdict before the assertion, and checkCachedAgyAuth correctly returns null. The assertion is racing the very TTL the test shrank. The second half of the test (the lapse) is fine; it's the pre-lapse assertion that is time-sensitive.
This is an intermittent failure at a fixed step, which is exactly the class that goes unreported because a rerun clears it — filing per house policy instead of just rerunning.
Suggested fix directions (builder's choice)
- Assert the pre-lapse state via the raw cache record (bypassing TTL evaluation), or
- Run the pre-lapse assertion under a generous TTL and only then re-record with the 50ms TTL for the lapse phase, or
- Inject a fake clock into the TTL check so the test controls time instead of sleeping against it.
Refs: PR #1588 (where it fired), #1077 (the regression the suite guards), #1323 (test-harness hygiene).
Symptom
Unit Tests(CI, ubuntu) failed once on PR #1588 headdb08a16b(run 33748523789, 2026-09-03), on a docs-only diff (two lines ofcodev/resources/arch.mdprose; zero source paths touched). Same suite passed on the previous head91f412bewith identical source. 1 failed / 5370 passed:Root cause (from the test source, not speculation)
The test pins
CODEV_AGY_AUTH_CACHE_TTL_UNAUTH_MS = '50'and then asserts the pre-lapse state through the TTL-checking reader:Any >50ms delay between the cache write inside
runLane(1)and line 325 (GC pause, loaded runner, coverage instrumentation) lapses the verdict before the assertion, andcheckCachedAgyAuthcorrectly returnsnull. The assertion is racing the very TTL the test shrank. The second half of the test (the lapse) is fine; it's the pre-lapse assertion that is time-sensitive.This is an intermittent failure at a fixed step, which is exactly the class that goes unreported because a rerun clears it — filing per house policy instead of just rerunning.
Suggested fix directions (builder's choice)
Refs: PR #1588 (where it fired), #1077 (the regression the suite guards), #1323 (test-harness hygiene).