[arm64] GC hole: JIT must kill the destination register right after adrp #136411

Re: #135794 (comment)

Found after enabling GC stress in R2R code.

On arm64, adrp+add (IF_LARGEADR) and adrp+ldr (IF_LARGELDC) are emitted as one emitter instruction (emitOutputLoadLabel/emitOutputLJ). GC liveness of the register written by adrp therefore can't change between the two machine instructions. If it held a live GC ref before the pair, it is still reported as one while it holds a non-GC page address.

In fully interruptible code a thread can be suspended at the second instruction, so this is a real GC hole, not just a GC stress artifact. R2R uses the pair (relocatable address) for the async ResumeInfo address (genAsyncResumeInfo).

Found via GC stress on R2R (#135794, #108249). The arm64 async.0.1 run (MutateImplicitByRef) took a SIGILL at add x0,x0,#0xdd8. x0 was reported as a GC ref holding an image page address, and Object::Validate crashed. This is from a core dump; the GC info was not decoded.

Fix: emit the GC kill for the register right after adrp, like the existing TLS-GD adrp case (emitGCregDeadUpd(REG_R0, dst)).