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[Arm64] ASIMD Polynomial Multiply Long #35143
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The following are omitted in #32512
class AdvSimd
{
/// <summary>
/// poly16x8_t vmull_p8 (poly8x8_t a, poly8x8_t b)
/// A32: VMULL.P8 Qd, Dn, Dm
/// A64: PMULL Vd.16B, Vn.8B, Vm.8B
/// </summary>
public static Vector128<sbyte> PolynomialMultiplyWideningLower(Vector64<sbyte> left, Vector64<sbyte> right);
/// <summary>
/// poly16x8_t vmull_p8 (poly8x8_t a, poly8x8_t b)
/// A32: VMULL.P8 Qd, Dn, Dm
/// A64: PMULL Vd.16B, Vn.8B, Vm.8B
/// </summary>
public static Vector128<byte> PolynomialMultiplyWideningLower(Vector64<byte> left, Vector64<byte> right);
/// <summary>
/// poly16x8_t vmull_high_p8 (poly8x16_t a, poly8x16_t b)
/// A32: VMULL.P8 Qd, Dn+1, Dm+1
/// A64: PMULL2 Vd.16B, Vn.16B, Vm.16B
/// </summary>
public static Vector128<sbyte> PolynomialMultiplyWideningUpper(Vector128<sbyte> left, Vector128<sbyte> right);
/// <summary>
/// poly16x8_t vmull_high_p8 (poly8x16_t a, poly8x16_t b)
/// A32: VMULL.P8 Qd, Dn+1, Dm+1
/// A64: PMULL2 Vd.16B, Vn.16B, Vm.16B
/// </summary>
public static Vector128<byte> PolynomialMultiplyWideningUpper(Vector128<byte> left, Vector128<byte> right);
}
class Aes
{
/// <summary>
/// poly128_t vmull_p64 (poly64_t a, poly64_t b)
/// A32: VMULL.P8 Qd, Dn, Dm
/// A64: PMULL Vd.1Q, Vn.1D, Vm.1D
/// </summary>
public static Vector128<long> PolynomialMultiplyWideningLower(Vector64<long> left, Vector64<long> right);
/// <summary>
/// poly128_t vmull_p64 (poly64_t a, poly64_t b)
/// A32: VMULL.P8 Qd, Dn, Dm
/// A64: PMULL Vd.1Q, Vn.1D, Vm.1D
/// </summary>
public static Vector128<ulong> PolynomialMultiplyWideningLower(Vector64<ulong> left, Vector64<ulong> right);
/// <summary>
/// poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
/// A32: VMULL.P8 Qd, Dn+1, Dm+1
/// A64: PMULL2 Vd.1Q, Vn.2D, Vm.2D
/// </summary>
public static Vector128<long> PolynomialMultiplyWideningUpper(Vector128<long> left, Vector128<long> right);
/// <summary>
/// poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
/// A32: VMULL.P8 Qd, Dn+1, Dm+1
/// A64: PMULL2 Vd.1Q, Vn.2D, Vm.2D
/// </summary>
public static Vector128<ulong> PolynomialMultiplyWideningUpper(Vector128<ulong> left, Vector128<ulong> right);
}There is also encoding PMULL Vd.1Q, Vn.1D, Vm.1D and PMULL2 Vd.1Q, Vn.2D, Vm.2D which
is only allocated in an implementation that includes the Cryptographic
Extension, and is otherwise RESERVED.
I wonder whether we want to expose these at all in .NET 5.0 - since they don't belong to ASIMD ISA?
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api-approvedAPI was approved in API review, it can be implementedAPI was approved in API review, it can be implementedarch-arm64area-System.Runtime.Intrinsics
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TamarChristinaArm commentedon Apr 20, 2020
hmm did we get
PMULitself already?echesakov commentedon Apr 20, 2020
Yes, I implemented it in #33889
TamarChristinaArm commentedon Apr 20, 2020
If you do, won't that require the rest of the
AESinstructions as well? Since they use the same feature bit.echesakov commentedon Apr 20, 2020
Good point - I think we have got all
AES,SHA1andSHA256implemented.Arm Architecture Reference Manual (A2.3 The Armv8 Cryptographic Extension) talks about Armv8 Cryptographic Extension and the features ARMv8.0-AES and ARMv8.0-SHA:
I wonder if this means that a full path, for example, to intrinsic
Sha1_FixedRotateshould includeCryptographicExtensionclass somewhere in the middle (i.e. beSystem.Runtime.Intrinsics.Arm.CryptographicExtension.Sha1.FixedRotate) sinceSha1is a subset of instructions (a feature) provided by Cryptographic Extension.Is my understanding correct, that
PMULLinstruction that operates on two 64-bit polynomials is going to be a part of theCryptographicExtensionbut neitherAesnorShafeatures?TamarChristinaArm commentedon Apr 21, 2020
Unfortunately the crypto landscape is quite complicated... And there seems to be a discrepancy between the descriptions of
Armv8.0-AandArmv8.2-A+. I've asked internally for someclarification.No,
CryptographicExtensionis just a made up term, it's not an actual extension. In that it has no feature bits of it's own.CryptographicExtensionforArmv8.0-AcontainsAESandSHA1but fromArmv8.2-A+the class is much bigger.If you look at the identification register in
ID_AA64ISAR0_EL1(sectionD13.2.53) you'll see thatPMULLcrypto instructions are defined as an optional part ofAESinArmv8(pageD13-3099of theErelease of the Arm ARM).So it belongs as part of
AES. I'll reply more once I get a response on the ambiguity betweenArmv8.0-AandArm8.2-A.echesakov commentedon Apr 21, 2020
@TamarChristinaArm Thanks for the clarification - I will update the proposal to have PMULL on two 64-bit polynomials under Aes.
TamarChristinaArm commentedon Apr 27, 2020
@echesakovMSFT It's been confirmed to me that indeed we expect people to implement
AESandPMULLtogether. At some point this will be updated in the Arm ARM, but this also matches withllvmandgccdo.echesakov commentedon Apr 27, 2020
@TamarChristinaArm Thanks for following up on this!
echesakov commentedon May 1, 2020
Updated the proposal to include
PMULL Vd.1Q, Vn.1D, Vm.1DandPMULL2 Vd.1Q, Vn.2D, Vm.2DunderAesclassI could not think about a better way of mapping
poly128_tto .NET type system other thanVector128<long>orVector128<ulong>terrajobst commentedon May 19, 2020