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Test failure JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd #70642
Description
Activity
I have a possible repro with:
COMPlus_JitStress=2 COMPlus_JitStressRegs=1 COMPlus_TieredCompilation=0
where
Beginning test case GreaterThanAll.UInt64 at 2022-06-14 17:38:28 Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Vector256.GreaterThanAll<UInt64>(Vector256<UInt64>, Vector256<UInt64>): RunClassLclFldScenario failed: left: (12637113584965165198, 11906490245067638421, 2675376867114167282, 15181280614834259551) right: (6060109143144987292, 7698818418307277769, 12987557598810895790, 15520906607743203200) result: (True) Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario ERROR!!!-System.Exception: One or more scenarios did not complete as expected.Failed again in: runtime-coreclr jitstress2-jitstressregs 20220618.1
Failed test:
coreclr windows x64 Checked jitstress2_jitstressregs1 @ Windows.10.Amd64.Open - JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd coreclr windows x64 Checked jitstress2_jitstressregs8 @ Windows.10.Amd64.Open - JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmdError message:
Return code: 1 Raw output file: C:\h\w\B60809B1\w\B80609AB\uploads\Reports\JIT.HardwareIntrinsics\General\Vector256\Vector256_ro\Vector256_ro.output.txt Raw output: BEGIN EXECUTION "C:\h\w\B60809B1\p\corerun.exe" -p "System.Reflection.Metadata.MetadataUpdater.IsSupported=false" Vector256_ro.dll Beginning test case Abs.Byte at 6/18/2022 7:38:22 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:22 PM Beginning test case Abs.Double at 6/18/2022 7:38:22 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:22 PM Beginning test case Abs.Int16 at 6/18/2022 7:38:22 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:23 PM Beginning test case Abs.Int32 at 6/18/2022 7:38:23 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:23 PM Beginning test case Abs.Int64 at 6/18/2022 7:38:23 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:23 PM Beginning test case Abs.SByte at 6/18/2022 7:38:23 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/18/2022 7:38:23 PM Beginning test case Abs.Single at 6/18/2022 7:38:23 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Begin Stack trace at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_cmd() at System.RuntimeMethodHandle.InvokeMethod(Object target, Void** arguments, Signature sig, Boolean isConstructor) at System.Reflection.MethodInvoker.Invoke(Object obj, IntPtr* args, BindingFlags invokeAttr)Failed again in: runtime-coreclr jitstress2-jitstressregs 20220626.1
Failed test:
coreclr windows x64 Checked jitstress2_jitstressregs1 @ Windows.10.Amd64.Open - JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd coreclr windows x64 Checked jitstress2_jitstressregs8 @ Windows.10.Amd64.Open - JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmdError message:
Return code: 1 Raw output file: C:\h\w\A53D091B\w\BCF80A22\uploads\Reports\JIT.HardwareIntrinsics\General\Vector256\Vector256_ro\Vector256_ro.output.txt Raw output: BEGIN EXECUTION "C:\h\w\A53D091B\p\corerun.exe" -p "System.Reflection.Metadata.MetadataUpdater.IsSupported=false" Vector256_ro.dll Beginning test case Abs.Byte at 6/26/2022 7:24:18 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:19 PM Beginning test case Abs.Double at 6/26/2022 7:24:19 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:19 PM Beginning test case Abs.Int16 at 6/26/2022 7:24:19 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:19 PM Beginning test case Abs.Int32 at 6/26/2022 7:24:19 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:19 PM Beginning test case Abs.Int64 at 6/26/2022 7:24:19 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:19 PM Beginning test case Abs.SByte at 6/26/2022 7:24:19 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Beginning scenario: RunClassFldScenario Beginning scenario: RunStructLclFldScenario Beginning scenario: RunStructFldScenario Ending test case at 6/26/2022 7:24:20 PM Beginning test case Abs.Single at 6/26/2022 7:24:20 PM Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro Beginning scenario: RunBasicScenario_UnsafeRead Beginning scenario: RunReflectionScenario_UnsafeRead Beginning scenario: RunClsVarScenario Beginning scenario: RunLclVarScenario_UnsafeRead Beginning scenario: RunClassLclFldScenario Begin Stack trace at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_cmd() at System.RuntimeMethodHandle.InvokeMethod(Object target, Void** arguments, Signature sig, Boolean isConstructor) at System.Reflection.MethodInvoker.Invoke(Object obj, IntPtr* args, BindingFlags invokeAttr)8 remaining items
The failure case is as @tannergooding mentioned above: #70642 (comment)
With this particular stress setup, some of the test cases are inlined into the "main" function
GreaterThanAllUInt64(), namely the failingtest.RunClassLclFldScenario();as well as one of its predecessors.In the inlined predecessor, we have
vpcmpeqd ymm10,ymm10,ymm10to generate-1in all lanes, from:t2300 = CNS_VEC simd32<0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff> REG mm10 $42In the inlined
RunClassLclFldScenario()we also need this value:Generating: N1131 ( 1, 2) [002433] ----------- t2433 = CNS_VEC simd32<0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff> REG mm10 $42 TreeNode is marked ReuseRegbut, as seen, because it is marked as
ReuseRegby the register allocator, we don't generate any code.The bug is, there was a call between definition of
ymm10and theReuseReguse, and only the lower half of the register was preserved (because the high part of x64 SIMD registers are not callee-saved, by the ABI definition). Thus,ymm10doesn't contain the correct value.The intermediate call doesn't have any specific kill of
ymm10since that's callee-saved (but only the low part):N1103 ( 15, 7) [002404] --CXG------ * CALL void JIT.HardwareIntrinsics.General.VectorBooleanBinaryOpTest__GreaterThanAllUInt64..ctor REG NA $VN.Void <RefPosition #1051 @1103 RefTypeFixedReg <Reg:rcx> BB13 regmask=[rcx] minReg=1 wt=6400.00> <RefPosition #1052 @1103 RefTypeUse <Ivl:230> BB13 regmask=[rcx] minReg=1 last fixed wt=6400.00> <RefPosition #1053 @1104 RefTypeKill <Reg:rax> BB13 regmask=[rax] minReg=1 wt=6400.00> <RefPosition #1054 @1104 RefTypeKill <Reg:rcx> BB13 regmask=[rcx] minReg=1 wt=6400.00> <RefPosition #1055 @1104 RefTypeKill <Reg:rdx> BB13 regmask=[rdx] minReg=1 wt=6400.00> <RefPosition #1056 @1104 RefTypeKill <Reg:r8 > BB13 regmask=[r8] minReg=1 wt=6400.00> <RefPosition #1057 @1104 RefTypeKill <Reg:r9 > BB13 regmask=[r9] minReg=1 wt=6400.00> <RefPosition #1058 @1104 RefTypeKill <Reg:r10> BB13 regmask=[r10] minReg=1 wt=6400.00> <RefPosition #1059 @1104 RefTypeKill <Reg:r11> BB13 regmask=[r11] minReg=1 wt=6400.00> <RefPosition #1060 @1104 RefTypeKill <Reg:mm0> BB13 regmask=[mm0] minReg=1 wt=6400.00> <RefPosition #1061 @1104 RefTypeKill <Reg:mm1> BB13 regmask=[mm1] minReg=1 wt=6400.00> <RefPosition #1062 @1104 RefTypeKill <Reg:mm2> BB13 regmask=[mm2] minReg=1 wt=6400.00> <RefPosition #1063 @1104 RefTypeKill <Reg:mm3> BB13 regmask=[mm3] minReg=1 wt=6400.00> <RefPosition #1064 @1104 RefTypeKill <Reg:mm4> BB13 regmask=[mm4] minReg=1 wt=6400.00> <RefPosition #1065 @1104 RefTypeKill <Reg:mm5> BB13 regmask=[mm5] minReg=1 wt=6400.00>Looks like there's some missing logic for ReuseReg and the FEATURE_PARTIAL_SIMD_CALLEE_SAVE case.
Introduced by #70171. Still investigating.
@BruceForstall and I spoke offline and as he pointed, there is a case missing where we need to either kill the upper-half of vector register if it was callee-save or save/restore if it was callee-thrash. We create ref positions during building the interval, but we won't know which register got assigned until we come to the register assignment. I will think little bit more and try out some ideas that Bruce suggested.
@kunalspathak Given that the fix will probably require significant new work, I think we should revert #70171 and port the revert to .NET 7. A new implementation with fix can be made in .NET 8.
@kunalspathak Given that the fix will probably require significant new work, I think we should revert #70171 and port the revert to .NET 7. A new implementation with fix can be made in .NET 8.
Yes, I was thinking on similar lines given that #70171 should be straightforward to revert. I will try few things for couple of hours and if they don't work, will submit a revert PR.
I expect the "right" fix might be something involving #70182.
For these types of constants, it is cheaper to reinitialize it entirely than to involve it with caller/callee save.
- For
ZeroandAllBitsSetwe havexorps tgtReg, tgtRegandpcmpeqd tgtReg, tgtReg - For other constants, we already have the entire 16 or 32-byte constant emitted as a CLS_VAR declaration
In both cases, avoiding spilling and opting to reconstitute the value directly will end up being "better" for the cases where a spill does happen.
- For
I expect the "right" fix might be something involving #70182.
Probably. As you know, currently, the problem is with #70171, we are doing opposite of reinitializing the constant, and instead trying to "reuse" it. In "reuse" case, we only save/restore upper half if it holds a live variable (and not constant as far as I can tell). I will see if we can patch the save/restore upper half criteria to include it. We might not able to piggyback on the kill refpositions to clear the constants (as I was discussing with Bruce) because the kill positions are per register and in our case, there is no kill refposition inserted for upper-half vector register.
Reacted by Tanner GoodingI will see if we can patch the save/restore upper half criteria to include it.
Hhhm, I cannot do that because the decision of saving/restore upper-half happens during interval building, while we won't know which register holds a constant (and hence need to be saved/restored) until register assignment.
- ghost locked as resolved and limited conversation to collaborators
on Sep 18, 2022
Run: runtime-coreclr jitstress2-jitstressregs 20220612.1
Failed test:
Error message: