crossgen2/VM layout mismatch in CI #73728

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1. ghost added

   area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

   on Aug 10, 2022
2. ghost added

   untriagedNew issue has not been triaged by the area ownerNew issue has not been triaged by the area owner

   on Aug 10, 2022
4. jakobbotsch

   added

   blocking-outerloopBlocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runsBlocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runs

   area-VM-coreclr

   and removed

   area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

   untriagedNew issue has not been triaged by the area ownerNew issue has not been triaged by the area owner

   on Aug 11, 2022
5. jakobbotsch commented on Aug 11, 2022

   

   jakobbotsch

   on Aug 11, 2022

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   Assert failure(PID 13708 [0x0000358c], Thread: 3532 [0x0dcc]): Verify_FieldOffset 'System.Text.Encodings.Web.OptimizedInboxTextEncoder._allowedAsciiCodePoints' Field offset 16!=24(actual) || baseOffset 8!=8(actual)
   
   CORECLR! LoadDynamicInfoEntry + 0x13D8 (0x00007ffc5e86b280) CORECLR! Module::FixupNativeEntry + 0x64 (0x00007ffc5e7eeb44)
   CORECLR! Module::FixupDelayListAux<Module ,int (__cdecl Module::)(READYTORUN_IMPORT_SECTION *,unsigned __int64,unsigned __int64 *,int)> + 0x204 (0x00007ffc5e92c43c) CORECLR! ReadyToRunInfo::GetEntryPoint + 0x2E8 (0x00007ffc5e92e218)
   CORECLR! MethodDesc::GetPrecompiledR2RCode + 0x48 (0x00007ffc5e8c76e0) CORECLR! MethodDesc::GetPrecompiledCode + 0x2C (0x00007ffc5e8c73f4)
   CORECLR! MethodDesc::PrepareILBasedCode + 0x260 (0x00007ffc5e8c9408) CORECLR! MethodDesc::PrepareCode + 0x54 (0x00007ffc5e8c919c)
   CORECLR! CodeVersionManager::PublishVersionableCodeIfNecessary + 0x354 (0x00007ffc5e811f64) CORECLR! MethodDesc::DoPrestub + 0x368 (0x00007ffc5e8c4ce8)
   File: D:\a_work\1\s\src\coreclr\vm\jitinterface.cpp Line: 13729
   Image: D:\h\w\BAA609FA\p\corerun.exe

   Not sure if this is a crossgen or VM problem.
6. jakobbotsch

   changed the title [-]jit\\regression\\jitblue\\runtime_60035\\runtime_60035\\runtime_60035.cmd[/-] [+]crossgen2/VM layout mismatch in CI[/+] on Aug 11, 2022
7. kunalspathak

   assigned

   trylek

   and

   mangod9

   on Aug 11, 2022
8. mangod9 commented on Aug 11, 2022

   

   mangod9

   on Aug 11, 2022

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   @trylek @davidwrighton is this related to a recent change?
9. JulieLeeMSFT

   added this to the 7.0.0 milestone on Aug 11, 2022
10. trylek commented on Aug 11, 2022

    

    trylek

    on Aug 11, 2022

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    This is certainly a Crossgen2 problem. David has a PR open for a layout fix, I'll investigate whether it also fixes this issue, otherwise I'm not aware of any recent Crossgen2 layout change.
11. mangod9

    removed

    blocking-outerloopBlocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runsBlocking the 'runtime-coreclr outerloop' and 'runtime-libraries-coreclr outerloop' runs

    on Aug 11, 2022
12. davidwrighton

    linked a pull request that will close this issueFix one more Crossgen2 field layout mismatch with runtime #73978on Aug 19, 2022
13. ghost added

    in-prThere is an active PR which will close this issue when it is mergedThere is an active PR which will close this issue when it is merged

    on Aug 19, 2022
14. trylek

    closed this as completedin #73978on Aug 20, 2022
15. ghost removed

    in-prThere is an active PR which will close this issue when it is mergedThere is an active PR which will close this issue when it is merged

    on Aug 20, 2022
16. ghost locked as resolved and limited conversation to collaborators on Sep 19, 2022