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Assertion failed 'refPosition->RegOptional()' #84747

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#84824
Closed
Assertion failed 'refPosition->RegOptional()'#84747
#84824
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kunalspathak
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JitStressCLR JIT issues involving JIT internal stress modesarch-arm64area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIblocking-clean-ci-optionalBlocking optional rolling runs
Milestone
8.0.0

Description

@BruceForstall
BruceForstall
opened on Apr 13, 2023

arm64 JitStress=2 JitStressRegs=8

https://dev.azure.com/dnceng-public/public/_build/results?buildId=235833&view=ms.vss-test-web.build-test-results-tab&runId=4502376&resultId=116940&paneView=dotnet-dnceng.dnceng-build-release-tasks.helix-test-information-tab

export DOTNET_TieredCompilation=0
export DOTNET_JitStress=2
export DOTNET_JitStressRegs=8

08:31:13.646 Running test: _AdvSimd_ro::JIT.HardwareIntrinsics.Arm._AdvSimd.Program.VectorLookupExtension_4_Byte()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario

Assert failure(PID 23 [0x00000017], Thread: 23 [0x0017]): Assertion failed 'refPosition->RegOptional()' in 'JIT.HardwareIntrinsics.Arm._AdvSimd.VectorLookupExtension_4Test__VectorTableLookupExtensionByte:RunLclVarScenario_UnsafeRead():this' during 'LSRA build intervals' (IL size 183; hash 0xb48fe709; FullOpts)

    File: /__w/1/s/src/coreclr/jit/lsra.cpp Line: 12369
    Image: /root/helix/work/correlation/corerun

[createdump] Gathering state for process 23 corerun
[createdump] Crashing thread 0017 signal 6 (0006)
apply_reg_state: ip and cfa unchanged; stopping here (ip=0xffeacda45230)
apply_reg_state: ip and cfa unchanged; stopping here (ip=0xffeacda45230)
apply_reg_state: ip and cfa unchanged; stopping here (ip=0xffeacda3a414)
[createdump] Writing crash report to file /home/helixbot/dotnetbuild/dumps/coredump.23.dmp.crashreport.json
[createdump] Crash report successfully written
[createdump] Writing minidump with heap to file /home/helixbot/dotnetbuild/dumps/coredump.23.dmp
[createdump] Written 279306240 bytes (68190 pages) to core file
[createdump] Target process is alive
[createdump] Dump successfully written in 594ms
[createdump] waitpid() returned successfully (wstatus 00000000)
App Exit Code: 22
Expected: 100
Actual: 22
END EXECUTION - FAILED

Activity

  1. BruceForstall
    added
    arch-arm64
    JitStressCLR JIT issues involving JIT internal stress modes
    area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
    blocking-clean-ci-optionalBlocking optional rolling runs
    on Apr 13, 2023
  2. BruceForstall
    added this to the 8.0.0 milestone on Apr 13, 2023
  3. BruceForstall
    assigned
    kunalspathak
    on Apr 13, 2023

  5. kunalspathak commented on Apr 13, 2023

    @kunalspathak
    kunalspathak
    on Apr 13, 2023
    Contributor

    This is an instance where we are not left with any candidates to assign to the definition of tbx because all the registers (10 of them) are busy at the previous location and are marked as delayFree.

    <RefPosition #747 @641 RefTypeUse <Ivl:1 V01> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #748 @641 RefTypeUpperVectorRestore <Ivl:62 (U02)> LCL_VAR BB07 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #749 @641 RefTypeUse <Ivl:2 V02> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #750 @641 RefTypeUpperVectorRestore <Ivl:63 (U03)> LCL_VAR BB07 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #751 @641 RefTypeUse <Ivl:3 V03> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #752 @641 RefTypeUpperVectorRestore <Ivl:64 (U04)> LCL_VAR BB07 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #753 @641 RefTypeUse <Ivl:4 V04> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #754 @641 RefTypeUpperVectorRestore <Ivl:65 (U05)> LCL_VAR BB07 regmask=[allFloat] minReg=1 wt=300.00>
<RefPosition #755 @641 RefTypeUse <Ivl:5 V05> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
<RefPosition #756 @641 RefTypeUse <Ivl:6 V06> LCL_VAR BB07 regmask=[allFloat] minReg=1 last wt=300.00>
Interval 164: simd8 RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #757 @642 RefTypeDef <Ivl:164> HWINTRINSIC BB07 regmask=[allFloat] minReg=1 wt=400.00>

    I think I will just extend my handling in #84588 to include the RefTypeDef as well.

  6. kunalspathak
    added a commit that references this issue on Apr 15, 2023

    Introduce isLiveAtConsecutiveRegistersLoc and fix dotnet#84747

    0d740b2
  7. kunalspathak
    closed this as completedin #84824on Apr 20, 2023
  8. kunalspathak
    added a commit that references this issue on Apr 20, 2023

    Various fixes for consecutive registers found with jitstressregs (#84824

    42acf9e
  9. ghost locked as resolved and limited conversation to collaborators on May 20, 2023
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