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Fix GC hole with rorx instruction #114467

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Merged
BruceForstall merged 1 commit into from
Apr 10, 2025
Merged

Fix GC hole with rorx instruction #114467

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6 changes: 6 additions & 0 deletions src/coreclr/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15331,8 +15331,14 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
{
case IF_RWR_ARD:

@tannergooding tannergooding Apr 10, 2025

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This and other places likely shouldn't be switching on the format at all. The emitfmtsxarch.h entries (https://github.com/dotnet/runtime/blob/main/src/coreclr/jit/emitfmtsxarch.h) all have relevant flags indicating whether given registers a read, write, or read-write (tracked via IS_INFO).

We should probably have this be, instead:

if (id->idIsReg1Write())
{
    emitGCregDeadUpd(id->idReg1(), dst);
}

if (id->idIsReg2Write())
{
    emitGCregDeadUpd(id->idReg2(), dst);
}

Technically we also define idIsReg3Write() and idIsReg4Write() for parity, but these are completely unused today and could be commented out.

Realistically we could be centralizing these checks for all instructions in some emitGCregDeadUpd(id, dst) helper given we don't need to be checking specific formats at all, which seems much more robust and less error prone.

case IF_RRW_ARD:
case IF_RWR_ARD_CNS:
case IF_RRW_ARD_CNS:
case IF_RWR_ARD_RRD:
case IF_RRW_ARD_RRD:
case IF_RWR_RRD_ARD:
case IF_RRW_RRD_ARD:
case IF_RWR_RRD_ARD_CNS:
case IF_RWR_RRD_ARD_RRD:
{
emitGCregDeadUpd(id->idReg1(), dst);
break;
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