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…arch neg/not/bswap are two-address on x86, but only binary nodes went through isRMWRegOper/getTgtPrefOperands, so LSRA never preferenced the operand of GT_NEG/GT_NOT/GT_BSWAP/GT_BSWAP16 to the destination and codegen had to emit a mov ahead of the instruction. No delayRegFree is needed here since there is no second operand that could be assigned the target register. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Copilot-Session: 6be3190f-5600-40ef-b306-56b5aac40070
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Pull request overview
This PR updates xarch LSRA’s operand preferencing so unary read-modify-write nodes (GT_NEG, GT_NOT, GT_BSWAP, GT_BSWAP16) preference their operand to the target register, allowing codegen to elide a pre-instruction mov in more cases.
Changes:
- Switch unary op handling in
LinearScan::BuildNodeto use a newBuildUnaryRMWUseshelper for RMW-form unary instructions. - Add
LinearScan::BuildUnaryRMWUsesto settgtPrefUsefor non-contained operands (mirroring the binary RMW preferencing behavior, withoutdelayRegFree). - Declare the new helper in
lsra.hunderTARGET_XARCH.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| src/coreclr/jit/lsraxarch.cpp | Prefer operand-to-dest for unary RMW nodes via new BuildUnaryRMWUses helper and extend handling to GT_BSWAP/GT_BSWAP16. |
| src/coreclr/jit/lsra.h | Add BuildUnaryRMWUses declaration for xarch LSRA build logic. |
This was referenced Aug 11, 2026
EgorBo
marked this pull request as ready for review
September 1, 2026 12:12
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Azure Pipelines: Successfully started running 6 pipeline(s). 10 pipeline(s) were filtered out due to trigger conditions. There may be pipelines that require an authorized user to comment /azp run to run. |
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| case GT_BSWAP: | ||
| case GT_BSWAP16: | ||
| // These are "bswap reg" / "ror reg.16, 8", which are RMW, unless the | ||
| // operand is contained, in which case we generate a "movbe reg, [mem]". | ||
| srcCount = BuildUnaryRMWUses(tree->gtGetOp1()); | ||
| BuildDef(tree); | ||
| break; |
This was referenced Sep 1, 2026
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🟢 Approval recommended
The change is small, xarch-scoped, and aligns LSRA operand preferencing with the two-address requirements of the affected unary instructions.
Review details
- Files reviewed: 2/2 changed files
- Comments generated: 1
- Review effort level: Lite
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| // Unlike the binary case handled by BuildRMWUses, there is no second operand that | ||
| // could be assigned the target register, so no `delayRegFree` is needed here; we | ||
| // only preference the operand to the target so that codegen can elide the "mov" | ||
| // that emitIns_BASE_R_R() would otherwise emit ahead of the instruction. |
This was referenced Sep 2, 2026
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neg/not/bswapare two-address on xarch, but only binary nodes go throughisRMWRegOper/getTgtPrefOperands, so LSRA never preferenced the operand ofGT_NEG/GT_NOT/GT_BSWAP/GT_BSWAP16to the destination and codegen had to emit amovahead of the instruction. Shifts already did this.No
delayRegFreeis needed since there is no second operand that could be assigned the target register.