Skip to content

Restore Windows Arm64 support for CPUs without LSE #132345

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
tannergooding merged 1 commit into from
Aug 15, 2026
+5 −11
Merged

Restore Windows Arm64 support for CPUs without LSE #132345

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/coreclr/nativeaot/Runtime/startup.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ bool DetectCPUFeatures()
{
#if defined(HOST_X86) || defined(HOST_AMD64)
PalPrintFatalError("\nThe current CPU is missing one or more of the following instruction sets: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT\n");
#elif defined(HOST_ARM64) && (defined(HOST_WINDOWS) || defined(HOST_OSX) || defined(HOST_MACCATALYST))
#elif defined(HOST_ARM64) && (defined(HOST_OSX) || defined(HOST_MACCATALYST))
PalPrintFatalError("\nThe current CPU is missing one or more of the following instruction sets: AdvSimd, LSE\n");
#elif defined(HOST_ARM64)
PalPrintFatalError("\nThe current CPU is missing one or more of the following instruction sets: AdvSimd\n");
Expand Down
6 changes: 0 additions & 6 deletions src/coreclr/tools/Common/InstructionSetHelpers.cs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -87,12 +87,6 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
{
// We require armv8-a everywhere
instructionSetSupportBuilder.AddSupportedInstructionSet("armv8-a");

if (targetOS == TargetOS.Windows)
{
// However, Windows also requires LSE
instructionSetSupportBuilder.AddSupportedInstructionSet("lse");
}
}
}
else if (targetArchitecture == TargetArchitecture.Wasm32)
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/vm/codeman.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1402,7 +1402,7 @@ void EEJitManager::SetCpuInfo()
{
#if defined(TARGET_X86) || defined(TARGET_AMD64)
EEPOLICY_HANDLE_FATAL_ERROR_WITH_MESSAGE(COR_E_EXECUTIONENGINE, W("\nThe current CPU is missing one or more of the following instruction sets: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT\n"));
#elif defined(TARGET_ARM64) && (defined(TARGET_WINDOWS) || defined(TARGET_OSX) || defined(TARGET_MACCATALYST))
#elif defined(TARGET_ARM64) && (defined(TARGET_OSX) || defined(TARGET_MACCATALYST))
EEPOLICY_HANDLE_FATAL_ERROR_WITH_MESSAGE(COR_E_EXECUTIONENGINE, W("\nThe current CPU is missing one or more of the following instruction sets: AdvSimd, LSE\n"));
#elif defined(TARGET_ARM64)
EEPOLICY_HANDLE_FATAL_ERROR_WITH_MESSAGE(COR_E_EXECUTIONENGINE, W("\nThe current CPU is missing one or more of the following instruction sets: AdvSimd\n"));
Expand Down
6 changes: 3 additions & 3 deletions src/native/minipal/cpufeatures.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -677,13 +677,13 @@ int minipal_getcpufeatures(void)
#endif // HOST_UNIX

#if defined(HOST_WINDOWS)
if (!IsProcessorFeaturePresent(PF_ARM_V8_INSTRUCTIONS_AVAILABLE) ||
!IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE))
if (!IsProcessorFeaturePresent(PF_ARM_V8_INSTRUCTIONS_AVAILABLE))
{
// One of the baseline ISAs is not supported
result |= IntrinsicConstants_Invalid;
}
else

if (IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE))
{
result |= ARM64IntrinsicConstants_Atomics;
}
Expand Down
Loading