APX - Improve NDD on latest Intel Hardware by kendall1997 · Pull Request #132727 · dotnet/runtime

kendall1997 · 2026-08-24T23:36:03Z

This pull request disables memory forms of NDD instructions for optimal performance on Intel CPUs with APX support.

Instruction selection and code generation improvements:

src/coreclr/jit/codegenxarch.cpp: Updated the eligibility check for NDD instructions in genCodeForBinary to exclude cases where the second operand is sourced from memory, ensuring NDD is used only for register and immediate sources.
src/coreclr/jit/emitxarch.cpp: Modified emitIns_BASE_R_R_RM to disable NDD instructions when the RM source operand is in memory, defaulting to a mov+op sequence instead.

…mance on latest Intel processors with APX

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Pull request overview

This PR adjusts x64 JIT instruction selection/emission to avoid generating the APX NDD (EVEX.ND) memory-source form, forcing a mov + binary-op sequence when the second source operand would come from memory.

Changes:

Tightened NDD eligibility in CodeGen::genCodeForBinary to exclude cases where op2 is sourced from memory.
Updated emitter::emitIns_BASE_R_R_RM to disable NDD when the RM operand is sourced from memory, falling back to mov+op.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.

File	Description
src/coreclr/jit/codegenxarch.cpp	Prevents NDD selection when operand 2 is a memory source in `genCodeForBinary`.
src/coreclr/jit/emitxarch.cpp	Prevents NDD move-elision + NDD emission when the RM source operand is memory in `emitIns_BASE_R_R_RM`.

Suppressed comments (1)

src/coreclr/jit/codegenxarch.cpp:1070

The new comment is Intel-specific ("latest Intel processors") but the condition only checks DoJitUseApxNDD (JitConfig.EnableApxNDD + encodability) and operand placement, not CPU vendor. This can be misleading documentation if APX/NDD ever becomes relevant beyond Intel.

Consider rewording the comment to describe the policy (disable memory-source form) without hard-coding a vendor claim unless the code actually checks for it.

        // On the latest Intel processors with APX, the memory form of NDD instructions has to be turned off by
        // default for optimal hardware performance, so keep NDD only for register and immediate sources.
        eligibleForNDD = emit->DoJitUseApxNDD(ins) && !op2->isUsedFromMemory();

+        // On the latest Intel processors with APX, the memory form of NDD instructions has to be turned off by
+        // default for optimal hardware performance, so keep NDD only for register and immediate sources.
+        eligibleForNDD = emit->DoJitUseApxNDD(ins) && !op2->isUsedFromMemory();


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Pull request overview

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Pull request overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.

+    // Disable the memory-source form of NDD (EVEX.ND) instructions for performance reasons; fall back to the
+    // mov+op sequence when the RM source is in memory.
+    bool useApxNdd = DoJitUseApxNDD(ins) && !rmOp->isUsedFromMemory();

    if (emitIns_Mov(INS_mov, attr, targetReg, regOp->GetRegNum(), true, useApxNdd) && useApxNdd)


kendall1997 · 2026-08-25T21:18:35Z

Hello @dotnet/intel, this PR is ready for your review! Thank you.

tannergooding · 2026-08-25T22:08:52Z

+        // For performance, avoid the memory-source form of EVEX.ND; keep NDD only for register and immediate sources.
+        eligibleForNDD = emit->DoJitUseApxNDD(ins) && !op2->isUsedFromMemory();


Can this be elaborated on a bit?

Is this saying it's avoiding ins dst, op1, [op2]? Can you elaborate more on why this is necessary and why it is or isn't a problem for ins dst, [op2] or for SIMD instructions?

This is going to bloat codegen and rather seems like it should be impacting lowering/lsra to ensure preferencing is correct, as otherwise we shouldn't have marked the operand as contained at all.

Hi @tannergooding, the tuning is based on performance results we observed on NVL. Similar tuning changes have also been upstreamed in both GCC and LLVM:

GCC: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a27731f6b52d94f4b1461709409057ab2a8a31ae

LLVM: [X86][APX] Enable NDD tunings llvm/llvm-project#186049

Thanks for your comment, I'll update the PR soon with the latest version of the change for your review!

…-memory-operand-public

The memory-source form of APX NDD (`ins dst, src1, [mem]`) is not profitable, so it is never selected; the legacy `mov dst, src1` + `ins dst, [mem]` pair is used instead. Register and immediate NDD forms are unchanged. Move the decision out of emitIns_BASE_R_R_RM into its two callers, genCodeForBinary and genCodeForMul, through a new DoJitUseApxNDD(ins, rmOp) overload, and pass it in explicitly. The emitter asserts the caller's choice, and that the fallback `mov` cannot overwrite an address register of the memory operand. LSRA guarantees the latter by modelling these nodes as read-modify-write. No codegen change when APX NDD is disabled (the default).

For read-modify-write nodes, BuildRMWUses marks op2 delay-free because the legacy sequence writes the destination before reading op2. The APX NDD form reads both sources first, so the constraint is not needed when codegen emits NDD. For an integer sub with a register op2, skip the delay-free when NDD is enabled for sub and op1 is a register-candidate local that stays live after the node. The destination can't take op1's register there, so the JIT already emitted the three-register NDD form; now the destination may take op2's register. Codegen emits NDD `sub dst, op1, op2` with dst == op2, and the emitter allows it. The op1 preference is unchanged, and a contained op2 keeps its delay-free. No codegen change when APX NDD is disabled (the default).

…emory-operand-public

Move the LSRA check that drops the op2 delay-free for APX NDD sub out of the else-if chain into a separate check under TARGET_AMD64, keyed on delayUseOperand. The condition is unchanged. In genCodeForBinary, let a non-commutative op whose destination got op2's register fall through to the three-register path, which already emits NDD. On the non-NDD path, a noway_assert keeps release builds from emitting a mov that would overwrite op2 if LSRA and codegen ever disagree. No codegen change.

Disable memory form of NDD instructions by default for optimal perfor…

dd4e338

…mance on latest Intel processors with APX

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kendall1997 marked this pull request as draft August 24, 2026 23:36

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build-analysis Bot mentioned this pull request Aug 25, 2026

Test failure: GC/Features/HeapExpansion/bestfit-finalize/bestfit-finalize.cmd #132107

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kendall1997 marked this pull request as ready for review August 25, 2026 19:22

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kendall1997 added 2 commits September 18, 2026 10:01

Merge remote-tracking branch 'upstream/main' into Kendall/ndd-without…

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…-memory-operand-public

Merge remote-tracking branch 'upstream/main' into Kendall/ndd-without…

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…-memory-operand-public

Ruihan-Yin mentioned this pull request Sep 30, 2026

Intel architecture improvements for .NET 12 #134986

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kendall1997 added 3 commits October 5, 2026 14:01

Merge remote-tracking branch 'origin/main' into Kendall/ndd-without-m…

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…emory-operand-public

kendall1997 marked this pull request as draft October 5, 2026 22:31

build-analysis Bot mentioned this pull request Oct 6, 2026

System.Net.Quic.QuicException : Connection handshake was canceled due to the configured timeout #133645

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build-analysis Bot mentioned this pull request Oct 6, 2026

[ci-scan] Hang: System.Diagnostics.Process.Tests times out on windows-x86 Checked CoreCLR #135001

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APX - Improve NDD on latest Intel Hardware - #132727

APX - Improve NDD on latest Intel Hardware#132727
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		// For performance, avoid the memory-source form of EVEX.ND; keep NDD only for register and immediate sources.
		eligibleForNDD = emit->DoJitUseApxNDD(ins) && !op2->isUsedFromMemory();

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