[RISC-V] NativeAOT soft-float target (riscv64-lp64) and builds without the A extension by maximmenshikov · Pull Request #134456 · dotnet/runtime

[RISC-V] Model the F, D, C and A extensions as instruction sets

maximmenshikov

committed

2347774

[RISC-V] Gate FP and compressed emission on the F and C instruction sets

maximmenshikov

committed

615c8a7

[RISC-V] Make the native build's ISA string and ABI configurable

maximmenshikov

committed

d645e95

[RISC-V] Apply the ISA string and ABI to the cross toolchain probes

maximmenshikov

committed

c207f6c

[RISC-V] Build libunwind for targets without the F/D extensions

maximmenshikov

committed

d8b9908

[RISC-V] Guard FP and atomic instructions in the assembly sources

maximmenshikov

committed

01310ba

[RISC-V] Tie the hwprobe assertion to the build's own -march

maximmenshikov

committed

f63476a

[RISC-V] Add the lp64 soft-float ABI to the JIT

maximmenshikov

committed

6399854

[RISC-V] Add the soft-float helpers and the riscv64-lp64 target

maximmenshikov

committed

3edf612

[RISC-V] Generate code for the soft-float target

maximmenshikov

committed

99ea61b

[RISC-V] Add a floating-point semantics test for the soft-float target

maximmenshikov

committed

c42bdf3

[RISC-V] Let a build select the lp64 ABI for NativeAOT publishing

maximmenshikov

committed

fed286d

[RISC-V] Pass -mabi=lp64 to the native linker and the shim compiler for riscv64-lp64

maximmenshikov

committed

6b75f50

[RISC-V] Lower Interlocked and CmpXchg without the A extension

maximmenshikov

committed

2fdd7d6

[RISC-V] Detect the A extension from the ISA string, and bump the JIT/EE GUID

maximmenshikov

committed

2dc1eb4

[RISC-V] Require --assume-no-concurrency to build without the A extension

maximmenshikov

committed

353000e

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[RISC-V] NativeAOT soft-float target (riscv64-lp64) and builds without the A extension - #134456

[RISC-V] NativeAOT soft-float target (riscv64-lp64) and builds without the A extension#134456
maximmenshikov wants to merge 16 commits into
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maximmenshikov:maximmenshikov/riscv64_zk_base

Commits on Sep 25, 2026

[RISC-V] Model the F, D, C and A extensions as instruction sets

[RISC-V] Gate FP and compressed emission on the F and C instruction sets

[RISC-V] Make the native build's ISA string and ABI configurable

[RISC-V] Apply the ISA string and ABI to the cross toolchain probes

[RISC-V] Build libunwind for targets without the F/D extensions

[RISC-V] Guard FP and atomic instructions in the assembly sources

[RISC-V] Tie the hwprobe assertion to the build's own -march

[RISC-V] Add the lp64 soft-float ABI to the JIT

[RISC-V] Add the soft-float helpers and the riscv64-lp64 target

[RISC-V] Generate code for the soft-float target

[RISC-V] Add a floating-point semantics test for the soft-float target

[RISC-V] Let a build select the lp64 ABI for NativeAOT publishing

[RISC-V] Pass -mabi=lp64 to the native linker and the shim compiler for riscv64-lp64

[RISC-V] Lower Interlocked and CmpXchg without the A extension

[RISC-V] Detect the A extension from the ISA string, and bump the JIT/EE GUID

[RISC-V] Require --assume-no-concurrency to build without the A extension