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Fix JIT over reporting RCPC2 #135134

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Merged
dhartglassMSFT merged 2 commits into from
Oct 5, 2026
Merged

Fix JIT over reporting RCPC2 #135134

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57832c5
initial impl
dhartglassMSFT Oct 2, 2026
ecebd5b
some comment rewording
dhartglassMSFT Oct 2, 2026
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18 changes: 12 additions & 6 deletions src/coreclr/jit/lower.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7684,11 +7684,11 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par
}

#ifdef TARGET_ARM64
if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile() &&
!m_compiler->compOpportunisticallyDependsOn(InstructionSet_Rcpc2))
if (parent->OperIs(GT_STOREIND) && parent->AsIndir()->IsVolatile() &&
m_compiler->codeGen->gcInfo.gcIsWriteBarrierStoreIndNode(parent->AsStoreInd()))
{
// For Arm64 we avoid using LEA for volatile INDs
// because we won't be able to use ldar/star
// Early out here so we don't report an RCPC2 dependency for a store that will ultimately
// be a write barrier instead of a volatile RCPC2 store
return false;
}

Expand Down Expand Up @@ -7734,8 +7734,6 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par
// Generally, we try to avoid creating addressing modes for volatile INDs so we can then use
// ldar/stlr instead of ldr/str + dmb. Although, with Arm 8.4+'s RCPC2 we can handle unscaled
// addressing modes (if the offset fits into 9 bits)
assert(m_compiler->compIsaSupportedDebugOnly(InstructionSet_Rcpc2));

if ((scale > 1) || (!emitter::emitIns_valid_imm_for_unscaled_ldst_offset(offset)) || (index != nullptr))
{
return false;
Expand Down Expand Up @@ -7771,6 +7769,14 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par
return false;
}

#ifdef TARGET_ARM64
if (parent->OperIsIndir() && parent->AsIndir()->IsVolatile() &&
!m_compiler->compOpportunisticallyDependsOn(InstructionSet_Rcpc2))
{
return false;
}
#endif

JITDUMP("Addressing mode:\n");
JITDUMP(" Base\n ");
DISPNODE(base);
Expand Down
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