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Merged
echesakov merged 33 commits into from
Mar 24, 2020
Merged

[Arm64] Implement more hardware intrinsics from #24794 #33889

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c27d4ee
Add MultiplyExtended and MultiplyExtendedScalar in AdvSimd.cs AdvSimd…
echesakov Mar 13, 2020
c0212bc
Add ReciprocalEstimate and ReciprocalEstimateScalar in AdvSimd.cs Adv…
echesakov Mar 13, 2020
89eebab
Add ReciprocalStep and ReciprocalStepScalar in AdvSimd.cs AdvSimd.Pla…
echesakov Mar 13, 2020
c6d6916
Add ReciprocalExponentScalar in AdvSimd.cs AdvSimd.PlatformNotSupport…
echesakov Mar 13, 2020
d9447e9
Add ReciprocalSquareRootEstimate and ReciprocalSquareRootEstimateScal…
echesakov Mar 13, 2020
74b7522
Add ReciprocalSquareRootStep and ReciprocalSquareRootStepScalar in Ad…
echesakov Mar 13, 2020
f3cdae5
Add PolynomialMultiply in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Mar 13, 2020
f09a3d1
Add AbsoluteDifferenceAdd in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Mar 13, 2020
f8da45f
Update System.Runtime.Intrinsics.Experimental.cs
echesakov Mar 18, 2020
396b4c5
Add MultiplyExtended in hwintrinsiclistarm64.h
echesakov Mar 17, 2020
5778c6b
Add Reciprocal* in hwintrinsiclistarm64.h
echesakov Mar 17, 2020
b8b3f26
Add PolynomialMultiply in hwintrinsiclistarm64.h
echesakov Mar 17, 2020
14cea9b
Add AbsoluteDifferenceAdd in hwintrinsiclistarm64.h
echesakov Mar 17, 2020
ebdafe1
Put fsqrt in alphabetic order in instrsarm64.h
echesakov Mar 18, 2020
2ab63c6
Add frecps, fqsqrts, frecpe, urecpe, ursqrte, frecpx in instrsarm64.h
echesakov Mar 18, 2020
50b3b0d
Add frecps, fqsqrts, frecpe, urecpe, ursqrte, frecpx in emitarm64.cpp
echesakov Mar 18, 2020
715b4d9
Update getInsExecutionCharacteristics() in emitarm64.cpp
echesakov Mar 18, 2020
cb23b5d
Remove NYI("Untested") assertion in emitarm64.cpp
echesakov Mar 18, 2020
386f448
Add unit tests for the newly added instrustions in codegenarm64.cpp
echesakov Mar 18, 2020
2f5dff7
Add unit tests for previously untested fcmeq,fcmge,fcmgt,fcmle,fcmlt …
echesakov Mar 18, 2020
9126f7b
Print zero immediate for fcmeq,fcmge,fcmgt,fcmle,fcmlt in emitDispIns…
echesakov Mar 18, 2020
01fdc17
Add missing BaseTypeFromFirstArg for AbsoluteDifference in hwintrinsi…
echesakov Mar 19, 2020
50fc3f4
Add MultiplyExtended in GenerateTests.csx
echesakov Mar 19, 2020
1ed3dd8
Add ReciprocalEstimate and ReciprocalEstimateScalar in GenerateTests.csx
echesakov Mar 19, 2020
e9e69d0
Add ReciprocalStep and ReciprocalStepScalar in GenerateTests.csx
echesakov Mar 19, 2020
5653a89
Add ReciprocalExponentScalar in GenerateTests.csx
echesakov Mar 19, 2020
71b040e
Add ReciprocalSquareRootEstimate and ReciprocalSquareRootEstimateScal…
echesakov Mar 19, 2020
4c73f25
Add ReciprocalSquareRootStep and ReciprocalSquareRootStepScalar in Ge…
echesakov Mar 19, 2020
ad0fe96
Add PolynomialMultiply in GenerateTests.csx
echesakov Mar 19, 2020
ef8a988
Add AbsoluteDifferenceAdd in GenerateTests.csx
echesakov Mar 19, 2020
e30a6c7
Update Helpers.cs Helpers.tt
echesakov Mar 19, 2020
94996c8
Update AdvSimd/ AdvSimd.Arm64/
echesakov Mar 20, 2020
9e7b2f1
Update BuildHWIntrinsic() to include AbsoluteDifferenceAdd in lsraarm…
echesakov Mar 20, 2020
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60 changes: 60 additions & 0 deletions src/coreclr/src/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7799,6 +7799,52 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_faddp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fcmeq Vd, Vn, #0.0
theEmitter->emitIns_R_R(INS_fcmeq, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_fcmeq, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE

// fcmge Vd, Vn, #0.0
theEmitter->emitIns_R_R(INS_fcmge, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_fcmge, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE

// fcmgt Vd, Vn, #0.0
theEmitter->emitIns_R_R(INS_fcmgt, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_fcmgt, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE

// fcmle Vd, Vn, #0.0
theEmitter->emitIns_R_R(INS_fcmle, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_fcmle, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE

// fcmlt Vd, Vn, #0.0
theEmitter->emitIns_R_R(INS_fcmlt, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_fcmlt, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE

// frecpe scalar
theEmitter->emitIns_R_R(INS_frecpe, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_frecpe, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE
theEmitter->emitIns_R_R(INS_frecpe, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_frecpe, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_frecpe, EA_16BYTE, REG_V8, REG_V9, INS_OPTS_2D);

// frecpx scalar
theEmitter->emitIns_R_R(INS_frecpx, EA_4BYTE, REG_V0, REG_V1);
theEmitter->emitIns_R_R(INS_frecpx, EA_8BYTE, REG_V2, REG_V3);

// frsqrte
theEmitter->emitIns_R_R(INS_frsqrte, EA_4BYTE, REG_V0, REG_V1); // scalar 4BYTE
theEmitter->emitIns_R_R(INS_frsqrte, EA_8BYTE, REG_V2, REG_V3); // scalar 8BYTE
theEmitter->emitIns_R_R(INS_frsqrte, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_frsqrte, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_frsqrte, EA_16BYTE, REG_V8, REG_V9, INS_OPTS_2D);

// urecpe vector
theEmitter->emitIns_R_R(INS_urecpe, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_urecpe, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_4S);

// ursqrte vector
theEmitter->emitIns_R_R(INS_ursqrte, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_ursqrte, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_4S);

// INS_fcvtl
theEmitter->emitIns_R_R(INS_fcvtl, EA_4BYTE, REG_V0, REG_V1);

Expand Down Expand Up @@ -7965,6 +8011,20 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_fabd, EA_16BYTE, REG_V9, REG_V10, REG_V11, INS_OPTS_4S);
theEmitter->emitIns_R_R_R(INS_fabd, EA_16BYTE, REG_V12, REG_V13, REG_V14, INS_OPTS_2D);

// frecps
theEmitter->emitIns_R_R_R(INS_frecps, EA_4BYTE, REG_V0, REG_V1, REG_V2); // scalar 4BYTE
theEmitter->emitIns_R_R_R(INS_frecps, EA_8BYTE, REG_V3, REG_V4, REG_V5); // scalar 8BYTE
theEmitter->emitIns_R_R_R(INS_frecps, EA_8BYTE, REG_V6, REG_V7, REG_V8, INS_OPTS_2S);
theEmitter->emitIns_R_R_R(INS_frecps, EA_16BYTE, REG_V9, REG_V10, REG_V11, INS_OPTS_4S);
theEmitter->emitIns_R_R_R(INS_frecps, EA_16BYTE, REG_V12, REG_V13, REG_V14, INS_OPTS_2D);

// frsqrts
theEmitter->emitIns_R_R_R(INS_frsqrts, EA_4BYTE, REG_V0, REG_V1, REG_V2); // scalar 4BYTE
theEmitter->emitIns_R_R_R(INS_frsqrts, EA_8BYTE, REG_V3, REG_V4, REG_V5); // scalar 8BYTE
theEmitter->emitIns_R_R_R(INS_frsqrts, EA_8BYTE, REG_V6, REG_V7, REG_V8, INS_OPTS_2S);
theEmitter->emitIns_R_R_R(INS_frsqrts, EA_16BYTE, REG_V9, REG_V10, REG_V11, INS_OPTS_4S);
theEmitter->emitIns_R_R_R(INS_frsqrts, EA_16BYTE, REG_V12, REG_V13, REG_V14, INS_OPTS_2D);

genDefineTempLabel(genCreateTempLabel());

theEmitter->emitIns_R_R_R(INS_fmul, EA_4BYTE, REG_V0, REG_V1, REG_V2); // scalar 4BYTE
Expand Down
62 changes: 55 additions & 7 deletions src/coreclr/src/jit/emitarm64.cpp
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4504,27 +4504,30 @@ void emitter::emitIns_R_R(
case INS_fcmgt:
case INS_fcmle:
case INS_fcmlt:
case INS_frecpe:
case INS_frsqrte:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));

if (isValidVectorDatasize(size))
if (insOptsAnyArrangement(opt))
{
// Vector operation
assert(insOptsAnyArrangement(opt));
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
elemsize = optGetElemsize(opt);
assert((elemsize == EA_8BYTE) || (elemsize == EA_4BYTE)); // Only Double/Float supported
assert(opt != INS_OPTS_1D); // Reserved encoding
assert(isValidVectorElemsizeFloat(elemsize)); // Only Double/Float supported
assert(opt != INS_OPTS_1D); // Reserved encoding
fmt = IF_DV_2A;
}
else
{
NYI("Untested");
// Scalar operation
assert((size == EA_8BYTE) || (size == EA_4BYTE)); // Only Double/Float supported
assert(isValidScalarDatasize(size)); // Only Double/Float supported
assert(insOptsNone(opt));
fmt = IF_DV_2G;
}
break;

case INS_aesd:
case INS_aese:
case INS_aesmc:
Expand Down Expand Up @@ -4586,6 +4589,25 @@ void emitter::emitIns_R_R(
fmt = IF_LS_2D;
break;

case INS_urecpe:
case INS_ursqrte:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
elemsize = optGetElemsize(opt);
assert(elemsize == EA_4BYTE);
fmt = IF_DV_2A;
break;

case INS_frecpx:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isValidScalarDatasize(size));
assert(insOptsNone(opt));
fmt = IF_DV_2G;
break;

default:
unreached();
break;
Expand Down Expand Up @@ -5532,6 +5554,8 @@ void emitter::emitIns_R_R_R(
case INS_fcmeq:
case INS_fcmge:
case INS_fcmgt:
case INS_frecps:
case INS_frsqrts:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isVectorRegister(reg3));
Expand Down Expand Up @@ -12151,7 +12175,16 @@ void emitter::emitDispIns(
case IF_DV_2L: // DV_2L ........XX...... ......nnnnnddddd Vd Vn (abs, neg - scalar)
elemsize = id->idOpSize();
emitDispReg(id->idReg1(), elemsize, true);
emitDispReg(id->idReg2(), elemsize, false);
if ((ins == INS_fcmeq) || (ins == INS_fcmge) || (ins == INS_fcmgt) || (ins == INS_fcmle) ||
(ins == INS_fcmlt))
{
emitDispReg(id->idReg2(), elemsize, true);
emitDispImm(0, false);
}
else
{
emitDispReg(id->idReg2(), elemsize, false);
}
break;

case IF_DV_2H: // DV_2H X........X...... ......nnnnnddddd Rd Vn (fmov, fcvtXX - to general)
Expand Down Expand Up @@ -13516,6 +13549,10 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_fcmgt:
case INS_fcmle:
case INS_fcmlt:
case INS_frecpe:
case INS_frsqrte:
case INS_urecpe:
case INS_ursqrte:
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
result.insLatency = PERFSCORE_LATENCY_2C;
break;
Expand Down Expand Up @@ -13580,6 +13617,13 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
result.insLatency = PERFSCORE_LATENCY_4C;
break;

case INS_frecpe:
case INS_frecpx:
case INS_frsqrte:
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
result.insLatency = PERFSCORE_LATENCY_4C;
break;

case INS_fsqrt:
if (id->idOpSize() == EA_8BYTE)
{
Expand Down Expand Up @@ -13629,6 +13673,8 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_fmulx:
case INS_fmla:
case INS_fmls:
case INS_frecps:
case INS_frsqrts:
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
result.insLatency = PERFSCORE_LATENCY_4C;
break;
Expand Down Expand Up @@ -13718,6 +13764,8 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_fmul:
case INS_fmulx:
case INS_fnmul:
case INS_frecps:
case INS_frsqrts:
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
result.insLatency = PERFSCORE_LATENCY_4C;
break;
Expand Down
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