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ggm-cuda: enforce DP4A MMQ tile height multiple of warp size - #30837
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JohannesGaessler merged 1 commit intoOct 23, 2026
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Added static assertion to enforce DP4A MMQ tile height requirement.
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@ggml-org/ggml-cuda Can you take a look at this ? Thanks :) |
am17an
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JohannesGaessler
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…g#30837) Added static assertion to enforce DP4A MMQ tile height requirement.
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…g#30837) Added static assertion to enforce DP4A MMQ tile height requirement.
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Overview
Add static assertion for DP4A MMQ tile height
Additional information
Will I was trying to tweak some mmq config, I try this config
CASE(GGML_TYPE_IQ4_NL, 512, 2, 96, 40, GGML_CUDA_MMQ_SRAM_LAYOUT_Q8_0, MMQ_ITER_K, false, true);this result in wrong computation and no test seems to detect this issue and the compiler accept it, as it should not.On gfx906, mmq use DP4A with 64 physical lanes, and in this loop:
With I=96 the loop use i0=0 and i0=64 but the integer division equals I/warp_size = 96/64 = 1.
For J40 with 512 threads (8 waves):
This static assert should avoid this mistake :)
Requirements