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Some SVE fixes for code generation #113860

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Merged
kunalspathak merged 5 commits into from
Mar 25, 2025
Merged

Some SVE fixes for code generation #113860

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b950776
standalone fix to generate sve mov instead of NEON mov
kunalspathak Mar 22, 2025
a9e9a9c
standalone fix to generate ldr/str when emit_RR is called
kunalspathak Mar 24, 2025
4535694
Remove unwanted change
kunalspathak Mar 24, 2025
f139bcf
Do not do sve_mov for scalar variant
kunalspathak Mar 25, 2025
427e35f
jit format fix
kunalspathak Mar 25, 2025
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9 changes: 8 additions & 1 deletion src/coreclr/jit/emitarm64sve.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2256,7 +2256,14 @@ void emitter::emitInsSve_R_R(instruction ins,
// Thus, MOV is the preferred disassembly.
ins = INS_sve_mov;
break;

case INS_sve_ldr:
case INS_sve_str:
{
// We might come here through emitIns_R_R() to emit "ldr Zx, [Xn]" and
// in the case, just generate the ldr variant, where offset is zero.
emitInsSve_R_R_I(ins, attr, reg1, reg2, 0, opt, sopt);
return;
}
default:
unreached();
break;
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4 changes: 2 additions & 2 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2561,8 +2561,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
assert(varTypeIsFloating(node->gtType) || varTypeIsSIMD(node->gtType));
assert((targetReg == op2Reg) || (targetReg != op1Reg));
assert((targetReg == op2Reg) || (targetReg != op3Reg));
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg,
/* canSkip */ true);

GetEmitter()->emitIns_Mov(INS_sve_mov, EA_SCALABLE, targetReg, op2Reg, /* canSkip */ true, opt);
GetEmitter()->emitInsSve_R_R_R(ins, EA_SCALABLE, targetReg, op1Reg, op3Reg, opt,
INS_SCALABLE_OPTS_WITH_SIMD_SCALAR);
break;
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